| Line 68... |
Line 68... |
//
|
//
|
`ifndef VERILATOR
|
`ifndef VERILATOR
|
`define OPT_STANDALONE
|
`define OPT_STANDALONE
|
`endif
|
`endif
|
//
|
//
|
|
//
|
|
// Two versions of the UART can be found in the rtl directory: a full featured
|
|
// UART, and a LITE UART that only handles 8N1 -- no break sending, break
|
|
// detection, parity error detection, etc. If we set USE_LITE_UART here, those
|
|
// simplified UART modules will be used.
|
|
//
|
|
// `define USE_LITE_UART
|
|
//
|
|
//
|
module echotest(i_clk,
|
module echotest(i_clk,
|
`ifndef OPT_STANDALONE
|
`ifndef OPT_STANDALONE
|
i_setup,
|
i_setup,
|
`endif
|
`endif
|
i_uart_rx, o_uart_tx);
|
i_uart_rx, o_uart_tx);
|
| Line 128... |
Line 137... |
//
|
//
|
// This code only applies if OPT_DUMBECHO is not defined.
|
// This code only applies if OPT_DUMBECHO is not defined.
|
wire rx_stb, rx_break, rx_perr, rx_ferr, rx_ignored;
|
wire rx_stb, rx_break, rx_perr, rx_ferr, rx_ignored;
|
wire [7:0] rx_data;
|
wire [7:0] rx_data;
|
|
|
|
`ifdef USE_LITE_UART
|
|
//
|
|
// NOTE: this depends upon the Verilator implementation using a setup
|
|
// of 868, since we cannot change the setup of the RXUARTLITE module.
|
|
//
|
|
rxuartlite #(24'd868)
|
|
receiver(i_clk, i_uart_rx, rx_stb, rx_data);
|
|
`else
|
rxuart receiver(i_clk, pwr_reset, i_setup, i_uart_rx, rx_stb, rx_data,
|
rxuart receiver(i_clk, pwr_reset, i_setup, i_uart_rx, rx_stb, rx_data,
|
rx_break, rx_perr, rx_ferr, rx_ignored);
|
rx_break, rx_perr, rx_ferr, rx_ignored);
|
|
`endif
|
|
|
// Bypass any transmit hardware flow control.
|
// Bypass any transmit hardware flow control.
|
wire rts;
|
wire cts_n;
|
assign rts = 1'b1;
|
assign cts_n = 1'b0;
|
|
|
wire tx_busy;
|
wire tx_busy;
|
|
`ifdef USE_LITE_UART
|
|
//
|
|
// NOTE: this depends upon the Verilator implementation using a setup
|
|
// of 868, since we cannot change the setup of the TXUARTLITE module.
|
|
//
|
|
txuartlite #(24'd868)
|
|
transmitter(i_clk, rx_stb, rx_data, o_uart_tx, tx_busy);
|
|
`else
|
txuart transmitter(i_clk, pwr_reset, i_setup, rx_break,
|
txuart transmitter(i_clk, pwr_reset, i_setup, rx_break,
|
rx_stb, rx_data, rts, o_uart_tx, tx_busy);
|
rx_stb, rx_data, rts, o_uart_tx, tx_busy);
|
|
`endif
|
|
|
`endif
|
`endif
|
|
|
endmodule
|
endmodule
|
|
|
