| Line 55... |
Line 55... |
o_uart_tx);
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o_uart_tx);
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//
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//
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input i_clk;
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input i_clk;
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output wire o_uart_tx;
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output wire o_uart_tx;
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`ifndef OPT_STANDALONE
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`ifndef OPT_STANDALONE
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input [29:0] i_setup;
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input [30:0] i_setup;
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`endif
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`endif
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// If i_setup isnt set up as an input parameter, it needs to be set.
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// If i_setup isnt set up as an input parameter, it needs to be set.
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// We do so here, to a setting appropriate to create a 115200 Baud
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// We do so here, to a setting appropriate to create a 115200 Baud
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// comms system from a 100MHz clock. This also sets us to an 8-bit
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// comms system from a 100MHz clock. This also sets us to an 8-bit
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// data word, 1-stop bit, and no parity.
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// data word, 1-stop bit, and no parity.
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`ifdef OPT_STANDALONE
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`ifdef OPT_STANDALONE
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wire [29:0] i_setup;
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wire [30:0] i_setup;
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assign i_setup = 30'd868; // 115200 Baud, if clk @ 100MHz
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assign i_setup = 31'd868; // 115200 Baud, if clk @ 100MHz
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`endif
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`endif
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|
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reg pwr_reset;
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reg pwr_reset;
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initial pwr_reset = 1'b1;
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initial pwr_reset = 1'b1;
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always @(posedge i_clk)
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always @(posedge i_clk)
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| Line 119... |
Line 119... |
if (&counter)
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if (&counter)
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tx_stb <= 1'b1;
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tx_stb <= 1'b1;
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else if ((tx_stb)&&(!tx_busy)&&(tx_index==4'hf))
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else if ((tx_stb)&&(!tx_busy)&&(tx_index==4'hf))
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tx_stb <= 1'b0;
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tx_stb <= 1'b0;
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|
|
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// Bypass any hardware flow control
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wire rts;
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assign rts = 1'b1;
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|
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txuart transmitter(i_clk, pwr_reset, i_setup, tx_break,
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txuart transmitter(i_clk, pwr_reset, i_setup, tx_break,
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tx_stb, tx_data, o_uart_tx, tx_busy);
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tx_stb, tx_data, rts, o_uart_tx, tx_busy);
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|
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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