| Line 54... |
Line 54... |
i_setup,
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i_setup,
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`endif
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`endif
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i_uart_rx, o_uart_tx);
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i_uart_rx, o_uart_tx);
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input i_clk;
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input i_clk;
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`ifndef OPT_STANDALONE
|
`ifndef OPT_STANDALONE
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input [29:0] i_setup;
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input [30:0] i_setup;
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`endif
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`endif
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input i_uart_rx;
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input i_uart_rx;
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output wire o_uart_tx;
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output wire o_uart_tx;
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|
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// If i_setup isnt set up as an input parameter, it needs to be set.
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// If i_setup isnt set up as an input parameter, it needs to be set.
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// We do so here, to a setting appropriate to create a 115200 Baud
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// We do so here, to a setting appropriate to create a 115200 Baud
|
// comms system from a 100MHz clock. This also sets us to an 8-bit
|
// comms system from a 100MHz clock. This also sets us to an 8-bit
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// data word, 1-stop bit, and no parity.
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// data word, 1-stop bit, and no parity.
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`ifdef OPT_STANDALONE
|
`ifdef OPT_STANDALONE
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wire [29:0] i_setup;
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wire [29:0] i_setup;
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assign i_setup = 30'd868; // 115200 Baud, if clk @ 100MHz
|
assign i_setup = 31'd868; // 115200 Baud, if clk @ 100MHz
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`endif
|
`endif
|
|
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reg [7:0] buffer [0:255];
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reg [7:0] buffer [0:255];
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reg [7:0] head, tail;
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reg [7:0] head, tail;
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|
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| Line 193... |
Line 193... |
if(pwr_reset)
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if(pwr_reset)
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tail <= 8'h00;
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tail <= 8'h00;
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else if ((tx_stb)&&(!tx_busy))
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else if ((tx_stb)&&(!tx_busy))
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tail <= tail + 8'h01;
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tail <= tail + 8'h01;
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|
|
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// Bypass any hardwaare flow control
|
|
wire rts;
|
|
assign rts = 1'b1;
|
|
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txuart transmitter(i_clk, pwr_reset, i_setup, tx_break,
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txuart transmitter(i_clk, pwr_reset, i_setup, tx_break,
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tx_stb, tx_data, o_uart_tx, tx_busy);
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tx_stb, tx_data, rts, o_uart_tx, tx_busy);
|
|
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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