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Line 39... |
//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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// Uncomment the next line if you want this program to work as a standalone
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// One issue with the design is how to set the values of the setup register.
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// (not verilated) RTL "program" to test your UART. You'll also need to set
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// (*This is a comment, not a verilator attribute ... ) Verilator needs to
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// your setup condition properly, though. I recommend setting it to the
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// know/set those values in order to work. However, this design can also be
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// ratio of your onboard clock to your desired baud rate. For more information
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// used as a stand-alone top level configuration file. In this latter case,
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// about how to set this, please see the specification.
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// the setup register needs to be set internal to the file. Here, we use
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// OPT_STANDALONE to distinguish between the two. If set, the file runs under
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// (* Another comment still ...) Verilator and we need to get i_setup from the
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// external environment. If not, it must be set internally.
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//
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//
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// `define OPT_STANDALONE
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`ifndef VERILATOR
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`define OPT_STANDALONE
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`endif
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//
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//
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module linetest(i_clk,
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module linetest(i_clk,
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`ifndef OPT_STANDALONE
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`ifndef OPT_STANDALONE
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i_setup,
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i_setup,
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`endif
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`endif
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Line 69... |
// If i_setup isnt set up as an input parameter, it needs to be set.
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// If i_setup isnt set up as an input parameter, it needs to be set.
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// We do so here, to a setting appropriate to create a 115200 Baud
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// We do so here, to a setting appropriate to create a 115200 Baud
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// comms system from a 100MHz clock. This also sets us to an 8-bit
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// comms system from a 100MHz clock. This also sets us to an 8-bit
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// data word, 1-stop bit, and no parity.
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// data word, 1-stop bit, and no parity.
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`ifdef OPT_STANDALONE
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`ifdef OPT_STANDALONE
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wire [29:0] i_setup;
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wire [30:0] i_setup;
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assign i_setup = 31'd868; // 115200 Baud, if clk @ 100MHz
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assign i_setup = 31'd868; // 115200 Baud, if clk @ 100MHz
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`endif
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`endif
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reg [7:0] buffer [0:255];
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reg [7:0] buffer [0:255];
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reg [7:0] head, tail;
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reg [7:0] head, tail;
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