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Line 52... |
//
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//
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`ifndef VERILATOR
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`ifndef VERILATOR
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`define OPT_STANDALONE
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`define OPT_STANDALONE
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`endif
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`endif
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//
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//
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//
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// Two versions of the UART can be found in the rtl directory: a full featured
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// UART, and a LITE UART that only handles 8N1 -- no break sending, break
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// detection, parity error detection, etc. If we set USE_LITE_UART here, those
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// simplified UART modules will be used.
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//
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// `define USE_LITE_UART
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//
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//
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module linetest(i_clk,
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module linetest(i_clk,
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`ifndef OPT_STANDALONE
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`ifndef OPT_STANDALONE
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i_setup,
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i_setup,
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`endif
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`endif
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i_uart_rx, o_uart_tx);
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i_uart_rx, o_uart_tx);
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Line 103... |
// frame errors will also be valid at that time. Finally, we'll ignore
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// frame errors will also be valid at that time. Finally, we'll ignore
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// errors, and even the clocked uart input distributed from here.
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// errors, and even the clocked uart input distributed from here.
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wire rx_stb, rx_break, rx_perr, rx_ferr, rx_ignored;
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wire rx_stb, rx_break, rx_perr, rx_ferr, rx_ignored;
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wire [7:0] rx_data;
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wire [7:0] rx_data;
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`ifdef USE_LITE_UART
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rxuartlite #(24'd868)
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receiver(i_clk, i_uart_rx, rx_stb, rx_data);
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`else
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rxuart receiver(i_clk, pwr_reset, i_setup, i_uart_rx, rx_stb, rx_data,
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rxuart receiver(i_clk, pwr_reset, i_setup, i_uart_rx, rx_stb, rx_data,
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rx_break, rx_perr, rx_ferr, rx_ignored);
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rx_break, rx_perr, rx_ferr, rx_ignored);
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`endif
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// The next step in this process is to dump everything we read into a
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// The next step in this process is to dump everything we read into a
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// FIFO. First step: writing into the FIFO. Always write into FIFO
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// FIFO. First step: writing into the FIFO. Always write into FIFO
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// memory. (The next step will step the memory address if rx_stb was
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// memory. (The next step will step the memory address if rx_stb was
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Line 213... |
tail <= 8'h00;
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tail <= 8'h00;
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else if ((tx_stb)&&(!tx_busy))
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else if ((tx_stb)&&(!tx_busy))
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tail <= tail + 8'h01;
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tail <= tail + 8'h01;
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// Bypass any hardwaare flow control
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// Bypass any hardwaare flow control
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wire rts;
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wire cts_n;
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assign rts = 1'b1;
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assign cts_n = 1'b0;
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`ifdef USE_LITE_UART
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txuartlite #(24'd868)
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transmitter(i_clk, tx_stb, tx_data, o_uart_tx, tx_busy);
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`else
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txuart transmitter(i_clk, pwr_reset, i_setup, tx_break,
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txuart transmitter(i_clk, pwr_reset, i_setup, tx_break,
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tx_stb, tx_data, rts, o_uart_tx, tx_busy);
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tx_stb, tx_data, cts_n, o_uart_tx, tx_busy);
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`endif
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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