OpenCores

Rev 15	Rev 18
Line 89...	Line 89...

`// Create a reset line that will always be true on a power on reset`	`// Create a reset line that will always be true on a power on reset`
`reg pwr_reset;`	`reg pwr_reset;`
`initial pwr_reset = 1'b1;`	`initial pwr_reset = 1'b1;`
`always @(posedge i_clk)`	`always @(posedge i_clk)`
`pwr_reset = 1'b0;`	`pwr_reset <= 1'b0;`



`// The UART Receiver`	`// The UART Receiver`
`//`	`//`
`// This is where everything begins, by reading data from the UART.`	`// This is where everything begins, by reading data from the UART.`
`//`	`//`
`// Data (rx_data) is present when rx_stb is true. Any parity or`	`// Data (rx_data) is present when rx_stb is true. Any parity or`
`// frame errors will also be valid at that time. Finally, we'll ignore`	`// frame errors will also be valid at that time. Finally, we'll ignore`
`// errors, and even the clocked uart input distributed from here.`	`// errors, and even the clocked uart input distributed from here.`
`wire rx_stb, rx_break, rx_perr, rx_ferr, rx_ignored;`	`wire rx_stb, rx_break, rx_perr, rx_ferr;`
	`/* verilator lint_off UNUSED */`
	`wire rx_ignored;`
	`/* verilator lint_on UNUSED */`
`wire [7:0] rx_data;`	`wire [7:0] rx_data;`

`ifdef USE_LITE_UART	`ifdef USE_LITE_UART
`rxuartlite #(24'd868)`	`rxuartlite #(24'd868)`
`receiver(i_clk, i_uart_rx, rx_stb, rx_data);`	`receiver(i_clk, i_uart_rx, rx_stb, rx_data);`

Line 89...

        // Create a reset line that will always be true on a power on reset

        // Create a reset line that will always be true on a power on reset

        reg     pwr_reset;

        reg     pwr_reset;

        initial pwr_reset = 1'b1;

        initial pwr_reset = 1'b1;

        always @(posedge i_clk)

        always @(posedge i_clk)

                pwr_reset = 1'b0;

                pwr_reset <= 1'b0;

        // The UART Receiver

        // The UART Receiver

//

//

        // This is where everything begins, by reading data from the UART.

        // This is where everything begins, by reading data from the UART.

//

//

        // Data (rx_data) is present when rx_stb is true.  Any parity or

        // Data (rx_data) is present when rx_stb is true.  Any parity or

        // frame errors will also be valid at that time.  Finally, we'll ignore

        // frame errors will also be valid at that time.  Finally, we'll ignore

        // errors, and even the clocked uart input distributed from here.

        // errors, and even the clocked uart input distributed from here.

        wire    rx_stb, rx_break, rx_perr, rx_ferr, rx_ignored;

        wire    rx_stb, rx_break, rx_perr, rx_ferr;

        /* verilator lint_off UNUSED */

        wire    rx_ignored;

        /* verilator lint_on UNUSED */

        wire    [7:0]    rx_data;

        wire    [7:0]    rx_data;

`ifdef  USE_LITE_UART

`ifdef  USE_LITE_UART

        rxuartlite #(24'd868)

        rxuartlite #(24'd868)

                receiver(i_clk, i_uart_rx, rx_stb, rx_data);

                receiver(i_clk, i_uart_rx, rx_stb, rx_data);

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