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//
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//
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// Purpose: To test that the txuart and rxuart modules work properly, by
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// Purpose: To test that the txuart and rxuart modules work properly, by
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// buffering one line's worth of input, and then piping that line
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// buffering one line's worth of input, and then piping that line
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// to the transmitter while (possibly) receiving a new line.
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// to the transmitter while (possibly) receiving a new line.
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//
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//
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// With some modifications (discussed below), this RTL should be able to
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// run as a top-level testing file, requiring only the transmit and receive
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// UART pins and the clock to work.
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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| Line 35... |
Line 39... |
//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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module linetest(i_clk, i_setup, i_uart, o_uart);
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// Uncomment the next line if you want this program to work as a standalone
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// (not verilated) RTL "program" to test your UART. You'll also need to set
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// your setup condition properly, though. I recommend setting it to the
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// ratio of your onboard clock to your desired baud rate. For more information
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// about how to set this, please see the specification.
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//
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// `define OPT_STANDALONE
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//
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module linetest(i_clk,
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`ifndef OPT_STANDALONE
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i_setup,
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`endif
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i_uart_rx, o_uart_tx);
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input i_clk;
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input i_clk;
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`ifndef OPT_STANDALONE
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input [29:0] i_setup;
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input [29:0] i_setup;
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input i_uart;
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`endif
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output wire o_uart;
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input i_uart_rx;
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output wire o_uart_tx;
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// If i_setup isnt set up as an input parameter, it needs to be set.
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// We do so here, to a setting appropriate to create a 115200 Baud
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// comms system from a 100MHz clock. This also sets us to an 8-bit
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// data word, 1-stop bit, and no parity.
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`ifdef OPT_STANDALONE
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wire [29:0] i_setup;
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assign i_setup = 30'd868; // 115200 Baud, if clk @ 100MHz
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`endif
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reg [7:0] buffer [0:255];
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reg [7:0] buffer [0:255];
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reg [7:0] head, tail;
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reg [7:0] head, tail;
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// Create a reset line that will always be true on a power on reset
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reg pwr_reset;
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reg pwr_reset;
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initial pwr_reset = 1'b1;
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initial pwr_reset = 1'b1;
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always @(posedge i_clk)
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always @(posedge i_clk)
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pwr_reset = 1'b0;
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pwr_reset = 1'b0;
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// The UART Receiver
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//
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// This is where everything begins, by reading data from the UART.
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//
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// Data (rx_data) is present when rx_stb is true. Any parity or
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// frame errors will also be valid at that time. Finally, we'll ignore
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// errors, and even the clocked uart input distributed from here.
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wire rx_stb, rx_break, rx_perr, rx_ferr, rx_ignored;
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wire rx_stb, rx_break, rx_perr, rx_ferr, rx_ignored;
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wire [7:0] rx_data;
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wire [7:0] rx_data;
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rxuart receiver(i_clk, pwr_reset, i_setup, i_uart, rx_stb, rx_data,
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rxuart receiver(i_clk, pwr_reset, i_setup, i_uart_rx, rx_stb, rx_data,
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rx_break, rx_perr, rx_ferr, rx_ignored);
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rx_break, rx_perr, rx_ferr, rx_ignored);
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// The next step in this process is to dump everything we read into a
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// FIFO. First step: writing into the FIFO. Always write into FIFO
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// memory. (The next step will step the memory address if rx_stb was
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// true ...)
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wire [7:0] nxt_head;
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wire [7:0] nxt_head;
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assign nxt_head = head + 8'h01;
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assign nxt_head = head + 8'h01;
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always @(posedge i_clk)
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always @(posedge i_clk)
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buffer[head] <= rx_data;
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buffer[head] <= rx_data;
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// Select where in our FIFO memory to write. On reset, we clear the
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// memory. In all other cases/respects, we step the memory forward.
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//
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// However ... we won't step it forward IF ...
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// rx_break - we are in a BREAK condition on the line
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// (i.e. ... it's disconnected)
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// rx_perr - We've seen a parity error
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// rx_ferr - Same thing for a frame error
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// nxt_head != tail - If the FIFO is already full, we'll just drop
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// this new value, rather than dumping random garbage
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// from the FIFO until we go round again ... i.e., we
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// don't write on potential overflow.
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//
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// Adjusting this address will make certain that the next write to the
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// FIFO goes to the next address--since we've already written the FIFO
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// memory at this address.
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initial head= 8'h00;
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initial head= 8'h00;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (pwr_reset)
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if (pwr_reset)
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head <= 8'h00;
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head <= 8'h00;
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else if ((rx_stb)&&(!rx_break)&&(!rx_perr)&&(!rx_ferr)&&(nxt_head != tail))
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else if ((rx_stb)&&(!rx_break)&&(!rx_perr)&&(!rx_ferr)&&(nxt_head != tail))
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| Line 71... |
Line 129... |
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wire [7:0] nused;
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wire [7:0] nused;
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reg [7:0] lineend;
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reg [7:0] lineend;
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reg run_tx;
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reg run_tx;
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// How much of the FIFO is in use? head - tail. What if they wrap
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// around? Still: head-tail, but this time truncated to the number of
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// bits of interest. It can never be negative ... so ... we're good,
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// this just measures that number.
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assign nused = head-tail;
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assign nused = head-tail;
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// Here's the guts of the algorithm--setting run_tx. Once set, the
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// buffer will flush. Here, we set it on one of two conditions: 1)
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// a newline is received, or 2) the line is now longer than 80
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// characters.
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//
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// Once the line has ben transmitted (separate from emptying the buffer)
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// we stop transmitting.
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initial run_tx = 0;
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initial run_tx = 0;
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initial lineend = 0;
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initial lineend = 0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (pwr_reset)
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if (pwr_reset)
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begin
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begin
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run_tx <= 1'b0;
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run_tx <= 1'b0;
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lineend <= 8'h00;
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lineend <= 8'h00;
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end else if ((rx_data == 8'h0a)&&(rx_stb))
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end else if(((rx_data == 8'h0a)||(rx_data == 8'hd))&&(rx_stb))
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begin
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begin
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// Start transmitting once we get to either a newline
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// or a carriage return character
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lineend <= head+8'h1;
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lineend <= head+8'h1;
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run_tx <= 1'b1;
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run_tx <= 1'b1;
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end else if ((!run_tx)&&(nused>8'd80)&&(head != tail))
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end else if ((!run_tx)&&(nused>8'd80))
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begin
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begin
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// Start transmitting once we get to 80 chars
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lineend <= head;
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lineend <= head;
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run_tx <= 1'b1;
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run_tx <= 1'b1;
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end else if (tail == lineend)
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end else if (tail == lineend)
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// Line buffer has been emptied
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run_tx <= 1'b0;
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run_tx <= 1'b0;
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// Now ... let's deal with the transmitter
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wire tx_break, tx_busy;
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wire tx_break, tx_busy;
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assign tx_break = 1'b0;
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assign tx_break = 1'b0;
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reg [7:0] tx_data;
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reg [7:0] tx_data;
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reg tx_stb;
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reg tx_stb;
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always @(posedge i_clk)
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// When do we wish to transmit?
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tx_data <= buffer[tail];
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//
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// Any time run_tx is true--but we'll give it an extra clock.
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initial tx_stb = 1'b0;
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initial tx_stb = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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tx_stb <= run_tx;
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tx_stb <= run_tx;
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// We'll transmit the data from our FIFO from ... wherever our tail
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// is pointed.
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always @(posedge i_clk)
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tx_data <= buffer[tail];
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// We increment the pointer to where we read from any time 1) we are
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// requesting to transmit a character, and 2) the transmitter was not
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// busy and thus accepted our request. At that time, increment the
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// pointer, and we'll be ready for another round.
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initial tail = 8'h00;
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initial tail = 8'h00;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if(pwr_reset)
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if(pwr_reset)
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tail <= 8'h00;
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tail <= 8'h00;
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else if ((tx_stb)&&(!tx_busy))
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else if ((tx_stb)&&(!tx_busy))
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tail <= tail + 8'h01;
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tail <= tail + 8'h01;
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txuart transmitter(i_clk, pwr_reset, i_setup, tx_break,
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txuart transmitter(i_clk, pwr_reset, i_setup, tx_break,
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tx_stb, tx_data, o_uart, tx_busy);
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tx_stb, tx_data, o_uart_tx, tx_busy);
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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