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Line 43... |
//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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// Uncomment the next line if you want this program to work as a standalone
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// One issue with the design is how to set the values of the setup register.
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// (not verilated) RTL "program" to test your UART. You'll also need to set
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// (*This is a comment, not a verilator attribute ... ) Verilator needs to
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// your i_setup condition properly, though (below). I recommend setting it to
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// know/set those values in order to work. However, this design can also be
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// the ratio of your onboard clock to your desired baud rate. For more
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// used as a stand-alone top level configuration file. In this latter case,
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// information about how to set this, please see the specification.
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// the setup register needs to be set internal to the file. Here, we use
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// OPT_STANDALONE to distinguish between the two. If set, the file runs under
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// (* Another comment still ...) Verilator and we need to get i_setup from the
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// external environment. If not, it must be set internally.
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//
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//
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//`define OPT_STANDALONE
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`ifndef VERILATOR
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`define OPT_STANDALONE
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`endif
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//
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//
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module speechfifo(i_clk,
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module speechfifo(i_clk,
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`ifndef OPT_STANDALONE
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`ifndef OPT_STANDALONE
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i_setup,
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i_setup,
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`endif
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`endif
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Line 68... |
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// Here we set i_setup to something appropriate to create a 115200 Baud
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// Here we set i_setup to something appropriate to create a 115200 Baud
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// UART system from a 100MHz clock. This also sets us to an 8-bit data
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// UART system from a 100MHz clock. This also sets us to an 8-bit data
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// word, 1-stop bit, and no parity. This will be overwritten by
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// word, 1-stop bit, and no parity. This will be overwritten by
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// i_setup, but at least it gives us something to start with/from.
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// i_setup, but at least it gives us something to start with/from.
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parameter INITIAL_UART_SETUP = 30'd868;
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parameter INITIAL_UART_SETUP = 31'd868;
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// The i_setup wires are input when run under Verilator, but need to
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// The i_setup wires are input when run under Verilator, but need to
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// be set internally if this is going to run as a standalone top level
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// be set internally if this is going to run as a standalone top level
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// test configuration.
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// test configuration.
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`ifdef OPT_STANDALONE
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`ifdef OPT_STANDALONE
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wire [29:0] i_setup;
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wire [30:0] i_setup;
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assign i_setup = INITIAL_UART_SETUP;
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assign i_setup = INITIAL_UART_SETUP;
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`else
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`else
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input [29:0] i_setup;
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input [30:0] i_setup;
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`endif
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`endif
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reg restart;
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reg restart;
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reg wb_stb;
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reg wb_stb;
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reg [1:0] wb_addr;
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reg [1:0] wb_addr;
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Line 107... |
// element to a space so that if (for some reason) we broadcast past the
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// element to a space so that if (for some reason) we broadcast past the
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// end of our message, we'll at least be sending something useful.
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// end of our message, we'll at least be sending something useful.
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integer i;
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integer i;
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reg [7:0] message [0:2047];
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reg [7:0] message [0:2047];
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initial begin
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initial begin
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// xx Verilator needs this file to be in the directory the file
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// is run from. For that reason, the project builds, makes,
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// and keeps speech.hex in bench/cpp.
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//
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// Vivado, however, wants speech.hex to be in a project file
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// directory, such as bench/verilog. For that reason, the
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// build function in bench/cpp also copies speech.hex to the
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// bench/verilog directory. You may need to make certain the
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// file is both built, and copied into a directory where your
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// synthesis tool can find it.
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//
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$readmemh("speech.hex",message);
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$readmemh("speech.hex",message);
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for(i=1481; i<2048; i=i+1)
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for(i=1481; i<2048; i=i+1)
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message[i] = 8'h20;
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message[i] = 8'h20;
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//
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// The problem with the above approach is Xilinx's ISE program.
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// It's broken. It can't handle HEX files well (at all?) and
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// has more problems with HEX's defining ROM's. For that
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// reason, the mkspeech program can be tuned to create an
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// include file, speech.inc. We include that program here.
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// It is rather ugly, though, and not a very elegant solution,
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// since it walks through every value in our speech, byte by
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// byte, with an initial line for each byte declaring what it
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// is to be.
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//
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// If you (need to) use this route, comment out both the
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// readmemh, the for loop, and the message[i] = 8'h20 lines
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// above and uncomment the include line below.
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//
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// `include "speech.inc"
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end
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end
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// Let's keep track of time, and send our message over and over again.
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// Let's keep track of time, and send our message over and over again.
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// To do this, we'll keep track of a restart counter. When this counter
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// To do this, we'll keep track of a restart counter. When this counter
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// rolls over, we restart our message.
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// rolls over, we restart our message.
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Line 190... |
if (restart)
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if (restart)
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// The first thing we do is set the baud rate, and
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// The first thing we do is set the baud rate, and
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// serial port configuration parameters. Ideally,
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// serial port configuration parameters. Ideally,
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// we'd only set this once. But rather than complicate
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// we'd only set this once. But rather than complicate
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// the logic, we set it everytime we start over.
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// the logic, we set it everytime we start over.
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wb_data <= { 2'b00, i_setup };
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wb_data <= { 1'b0, i_setup };
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else if ((wb_stb)&&(!uart_stall))
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else if ((wb_stb)&&(!uart_stall))
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// Then, if the last thing was received over the bus,
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// Then, if the last thing was received over the bus,
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// we move to the next data item.
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// we move to the next data item.
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wb_data <= { 24'h00, message[msg_index] };
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wb_data <= { 24'h00, message[msg_index] };
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| Line 206... |
Line 238... |
wb_stb <= 1'b1;
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wb_stb <= 1'b1;
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else if (end_of_message)
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else if (end_of_message)
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// Stop transmitting when we get to the end of our
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// Stop transmitting when we get to the end of our
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// message.
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// message.
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wb_stb <= 1'b0;
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wb_stb <= 1'b0;
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else if (tx_int)
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// If we aren't at the end of the message, and tx_int
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// tells us the FIFO is empty, then start writing into
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// the FIFO>
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wb_stb <= 1'b1;
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else if (txfifo_int)
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else if (txfifo_int)
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// If we are writing into the FIFO, and it's less than
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// If the FIFO is less than half full, then write to
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// half full (i.e. txfifo_int is true) then keep going.
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// it.
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wb_stb <= wb_stb;
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wb_stb <= 1'b1;
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else
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else
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// But once the FIFO gets to half full, stop.
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// But once the FIFO gets to half full, stop.
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wb_stb <= 1'b0;
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wb_stb <= 1'b0;
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// We aren't using the receive interrupts, so we'll just mark them
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// We aren't using the receive interrupts, so we'll just mark them
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// here as ignored.
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// here as ignored.
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wire ignored_rx_int, ignored_rxfifo_int;
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wire ignored_rx_int, ignored_rxfifo_int;
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// The WBUART can handle hardware flow control signals. This test,
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// however, cannot. The reason? Simply just to keep things simple.
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// If you want to add hardware flow control to your design, simply
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// make rts an input to this module.
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//
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// Since this is an output only module demonstrator, what would be the
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// cts output is unused.
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wire rts, cts;
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assign rts = 1'b1;
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// Finally--the unit under test--now that we've set up all the wires
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// Finally--the unit under test--now that we've set up all the wires
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// to run/test it.
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// to run/test it.
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wbuart #(INITIAL_UART_SETUP)
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wbuart #(INITIAL_UART_SETUP)
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wbuarti(i_clk, pwr_reset,
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wbuarti(i_clk, pwr_reset,
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wb_stb, wb_stb, 1'b1, wb_addr, wb_data,
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wb_stb, wb_stb, 1'b1, wb_addr, wb_data,
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uart_stall, uart_ack, uart_data,
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uart_ack, uart_stall, uart_data,
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1'b1, o_uart_tx,
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1'b1, o_uart_tx, rts, cts,
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ignored_rx_int, tx_int,
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ignored_rx_int, tx_int,
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ignored_rxfifo_int, txfifo_int);
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ignored_rxfifo_int, txfifo_int);
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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