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Line 257... |
// If you want to add hardware flow control to your design, simply
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// If you want to add hardware flow control to your design, simply
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// make rts an input to this module.
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// make rts an input to this module.
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//
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//
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// Since this is an output only module demonstrator, what would be the
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// Since this is an output only module demonstrator, what would be the
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// cts output is unused.
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// cts output is unused.
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wire rts, cts;
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wire cts_n, rts_n_ignored;
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assign rts = 1'b1;
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assign cts_n = 1'b0;
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// Finally--the unit under test--now that we've set up all the wires
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// Finally--the unit under test--now that we've set up all the wires
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// to run/test it.
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// to run/test it.
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wbuart #(INITIAL_UART_SETUP)
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wbuart #(INITIAL_UART_SETUP)
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wbuarti(i_clk, pwr_reset,
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wbuarti(i_clk, pwr_reset,
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wb_stb, wb_stb, 1'b1, wb_addr, wb_data,
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wb_stb, wb_stb, 1'b1, wb_addr, wb_data,
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uart_ack, uart_stall, uart_data,
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uart_ack, uart_stall, uart_data,
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1'b1, o_uart_tx, rts, cts,
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1'b1, o_uart_tx, cts_n, rts_n_ignored,
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ignored_rx_int, tx_int,
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ignored_rx_int, tx_int,
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ignored_rxfifo_int, txfifo_int);
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ignored_rxfifo_int, txfifo_int);
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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