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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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// Copyright (C) 2015-2017, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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// UART system from a 100MHz clock. This also sets us to an 8-bit data
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// UART system from a 100MHz clock. This also sets us to an 8-bit data
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// word, 1-stop bit, and no parity. This will be overwritten by
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// word, 1-stop bit, and no parity. This will be overwritten by
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// i_setup, but at least it gives us something to start with/from.
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// i_setup, but at least it gives us something to start with/from.
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parameter INITIAL_UART_SETUP = 31'd868;
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parameter INITIAL_UART_SETUP = 31'd868;
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// Let's set our message length, in case we ever wish to change it in
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// the future
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localparam MSGLEN=2203;
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// The i_setup wires are input when run under Verilator, but need to
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// The i_setup wires are input when run under Verilator, but need to
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// be set internally if this is going to run as a standalone top level
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// be set internally if this is going to run as a standalone top level
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// test configuration.
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// test configuration.
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`ifdef OPT_STANDALONE
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`ifdef OPT_STANDALONE
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wire [30:0] i_setup;
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wire [30:0] i_setup;
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reg restart;
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reg restart;
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reg wb_stb;
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reg wb_stb;
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reg [1:0] wb_addr;
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reg [1:0] wb_addr;
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reg [31:0] wb_data;
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reg [31:0] wb_data;
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wire uart_stall, uart_ack;
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wire uart_stall;
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// We aren't using the receive interrupts, or the received data, or the
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// ready to send line, so we'll just mark them all here as ignored.
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/* verilator lint_off UNUSED */
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wire uart_ack, tx_int;
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wire [31:0] uart_data;
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wire [31:0] uart_data;
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wire ignored_rx_int, ignored_rxfifo_int;
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wire rts_n_ignored;
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/* verilator lint_on UNUSED */
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wire tx_int, txfifo_int;
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/* verilator lint_on UNUSED */
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wire txfifo_int;
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// The next four lines create a strobe signal that is true on the first
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// The next four lines create a strobe signal that is true on the first
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// clock, but never after. This makes for a decent power-on reset
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// clock, but never after. This makes for a decent power-on reset
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// signal.
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// signal.
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reg pwr_reset;
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reg pwr_reset;
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//
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//
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// Since the message has fewer than 2048 elements in it, we preset every
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// Since the message has fewer than 2048 elements in it, we preset every
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// element to a space so that if (for some reason) we broadcast past the
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// element to a space so that if (for some reason) we broadcast past the
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// end of our message, we'll at least be sending something useful.
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// end of our message, we'll at least be sending something useful.
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integer i;
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integer i;
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reg [7:0] message [0:2047];
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reg [7:0] message [0:4095];
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initial begin
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initial begin
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// xx Verilator needs this file to be in the directory the file
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// xx Verilator needs this file to be in the directory the file
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// is run from. For that reason, the project builds, makes,
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// is run from. For that reason, the project builds, makes,
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// and keeps speech.hex in bench/cpp.
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// and keeps speech.hex in bench/cpp.
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//
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//
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// bench/verilog directory. You may need to make certain the
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// bench/verilog directory. You may need to make certain the
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// file is both built, and copied into a directory where your
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// file is both built, and copied into a directory where your
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// synthesis tool can find it.
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// synthesis tool can find it.
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//
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//
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$readmemh("speech.hex", message);
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$readmemh("speech.hex", message);
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for(i=1481; i<2048; i=i+1)
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for(i=MSGLEN; i<4095; i=i+1)
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message[i] = 8'h20;
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message[i] = 8'h20;
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//
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//
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// The problem with the above approach is Xilinx's ISE program.
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// The problem with the above approach is Xilinx's ISE program.
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// It's broken. It can't handle HEX files well (at all?) and
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// It's broken. It can't handle HEX files well (at all?) and
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// has more problems with HEX's defining ROM's. For that
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// has more problems with HEX's defining ROM's. For that
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// reason, the mkspeech program can be tuned to create an
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// reason, the mkspeech program can be tuned to create an
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// Our message index. This is the address of the character we wish to
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// Our message index. This is the address of the character we wish to
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// transmit next. Note, there's a clock delay between setting this
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// transmit next. Note, there's a clock delay between setting this
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// index and when the wb_data is valid. Hence, we set the index on
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// index and when the wb_data is valid. Hence, we set the index on
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// restart[0] to zero.
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// restart[0] to zero.
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reg [10:0] msg_index;
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reg [11:0] msg_index;
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initial msg_index = 11'd2040;
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initial msg_index = 12'h000 - 12'h8;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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if (restart)
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if (restart)
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msg_index <= 0;
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msg_index <= 0;
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else if ((wb_stb)&&(!uart_stall))
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else if ((wb_stb)&&(!uart_stall))
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initial end_of_message = 1'b1;
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initial end_of_message = 1'b1;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (restart)
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if (restart)
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end_of_message <= 1'b0;
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end_of_message <= 1'b0;
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else
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else
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end_of_message <= (msg_index >= 1481);
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end_of_message <= (msg_index >= MSGLEN);
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// The wb_stb signal indicates that we wish to write, using the wishbone
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// The wb_stb signal indicates that we wish to write, using the wishbone
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// to our peripheral. We have two separate types of writes. First,
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// to our peripheral. We have two separate types of writes. First,
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// we wish to write our setup. Then we want to drop STB and write
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// we wish to write our setup. Then we want to drop STB and write
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// our data. Once we've filled half of the FIFO, we wait for the FIFO
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// our data. Once we've filled half of the FIFO, we wait for the FIFO
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wb_stb <= 1'b1;
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wb_stb <= 1'b1;
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else
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else
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// But once the FIFO gets to half full, stop.
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// But once the FIFO gets to half full, stop.
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wb_stb <= 1'b0;
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wb_stb <= 1'b0;
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// We aren't using the receive interrupts, so we'll just mark them
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// here as ignored.
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wire ignored_rx_int, ignored_rxfifo_int;
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// The WBUART can handle hardware flow control signals. This test,
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// The WBUART can handle hardware flow control signals. This test,
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// however, cannot. The reason? Simply just to keep things simple.
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// however, cannot. The reason? Simply just to keep things simple.
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// If you want to add hardware flow control to your design, simply
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// If you want to add hardware flow control to your design, simply
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// make rts an input to this module.
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// make rts an input to this module.
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//
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//
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// Since this is an output only module demonstrator, what would be the
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// Since this is an output only module demonstrator, what would be the
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// cts output is unused.
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// cts output is unused.
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wire cts_n, rts_n_ignored;
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wire cts_n;
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assign cts_n = 1'b0;
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assign cts_n = 1'b0;
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// Finally--the unit under test--now that we've set up all the wires
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// Finally--the unit under test--now that we've set up all the wires
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// to run/test it.
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// to run/test it.
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wbuart #(INITIAL_UART_SETUP)
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wbuart #(INITIAL_UART_SETUP)
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