| Line 59... |
Line 59... |
`endif
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`endif
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o_uart_tx);
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o_uart_tx);
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input i_clk;
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input i_clk;
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output wire o_uart_tx;
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output wire o_uart_tx;
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// Here we set i_setup to something appropriate to create a 115200 Baud
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// UART system from a 100MHz clock. This also sets us to an 8-bit data
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// word, 1-stop bit, and no parity. This will be overwritten by
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// i_setup, but at least it gives us something to start with/from.
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parameter INITIAL_UART_SETUP = 30'd868;
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// The i_setup wires are input when run under Verilator, but need to
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// The i_setup wires are input when run under Verilator, but need to
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// be set internally if this is going to run as a standalone top level
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// be set internally if this is going to run as a standalone top level
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// test configuration.
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// test configuration.
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`ifdef OPT_STANDALONE
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`ifdef OPT_STANDALONE
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wire [29:0] i_setup;
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wire [29:0] i_setup;
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assign i_setup = INITIAL_UART_SETUP;
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// Here we set i_setup to something appropriate to create a 115200 Baud
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// UART system from a 100MHz clock. This also sets us to an 8-bit data
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// word, 1-stop bit, and no parity.
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assign i_setup = 30'd868;
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`else
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`else
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input [29:0] i_setup;
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input [29:0] i_setup;
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`endif
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`endif
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reg restart;
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reg wb_stb;
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reg wb_stb;
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reg [1:0] wb_addr;
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reg [1:0] wb_addr;
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reg [31:0] wb_data;
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reg [31:0] wb_data;
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wire uart_stall, uart_ack;
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wire uart_stall, uart_ack;
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| Line 99... |
Line 102... |
// element to a space so that if (for some reason) we broadcast past the
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// element to a space so that if (for some reason) we broadcast past the
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// end of our message, we'll at least be sending something useful.
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// end of our message, we'll at least be sending something useful.
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integer i;
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integer i;
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reg [7:0] message [0:2047];
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reg [7:0] message [0:2047];
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initial begin
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initial begin
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for(i=0; i<2048; i=i+1)
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message[i] = 8'h20;
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$readmemh("speech.hex",message);
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$readmemh("speech.hex",message);
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for(i=1481; i<2048; i=i+1)
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message[i] = 8'h20;
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end
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end
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// Let's keep track of time, and send our message over and over again.
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// Let's keep track of time, and send our message over and over again.
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// To do this, we'll keep track of a restart counter. When this counter
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// To do this, we'll keep track of a restart counter. When this counter
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// rolls over, we restart our message.
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// rolls over, we restart our message.
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| Line 119... |
Line 122... |
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// Ok, now that we have a counter that tells us when to start over,
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// Ok, now that we have a counter that tells us when to start over,
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// let's build a set of signals that we can use to get things started
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// let's build a set of signals that we can use to get things started
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// again. This will be the restart signal. On this signal, we just
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// again. This will be the restart signal. On this signal, we just
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// restart everything.
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// restart everything.
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reg restart;
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initial restart = 0;
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initial restart = 0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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restart <= (restart_counter == 0);
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restart <= (restart_counter == 0);
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end
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// Our message index. This is the address of the character we wish to
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// Our message index. This is the address of the character we wish to
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// transmit next. Note, there's a clock delay between setting this
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// transmit next. Note, there's a clock delay between setting this
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// index and when the wb_data is valid. Hence, we set the index on
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// index and when the wb_data is valid. Hence, we set the index on
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// restart[0] to zero.
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// restart[0] to zero.
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| Line 173... |
Line 173... |
if (restart)
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if (restart)
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wb_addr <= 2'b00;
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wb_addr <= 2'b00;
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else // if (!uart_stall)??
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else // if (!uart_stall)??
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wb_addr <= 2'b11;
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wb_addr <= 2'b11;
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// Knowing when to stop sending the speech is important, but depends
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// upon an 11 bit comparison. Since FPGA logic is best measured by the
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// number of inputs to an always block, we pull those 11-bits out of
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// the always block for wb_stb, and place them here on the clock prior.
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// If end_of_message is true, then we need to stop transmitting, and
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// wait for the next (restart) to get us started again. We set that
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// flag hee.
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reg end_of_message;
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initial end_of_message = 1'b1;
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always @(posedge i_clk)
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if (restart)
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end_of_message <= 1'b0;
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else
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end_of_message <= (msg_index >= 1481);
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// The wb_stb signal indicates that we wish to write, using the wishbone
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// The wb_stb signal indicates that we wish to write, using the wishbone
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// to our peripheral. We have two separate types of writes. First,
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// to our peripheral. We have two separate types of writes. First,
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// we wish to write our setup. Then we want to drop STB and write
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// we wish to write our setup. Then we want to drop STB and write
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// our data. Once we've filled half of the FIFO, we wait for the FIFO
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// our data. Once we've filled half of the FIFO, we wait for the FIFO
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// to empty before issuing a STB again and then fill up half the FIFO
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// to empty before issuing a STB again and then fill up half the FIFO
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// again.
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// again.
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initial wb_stb = 1'b0;
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initial wb_stb = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (restart)
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if (restart)
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// Start sending to the UART on a reset. The first
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// thing we'll send will be the configuration, but
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// that's done elsewhere. This just starts up the
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// writes to the peripheral wbuart.
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wb_stb <= 1'b1;
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wb_stb <= 1'b1;
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else if (msg_index >= 1481)
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else if (end_of_message)
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// Stop transmitting when we get to the end of our
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// message.
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wb_stb <= 1'b0;
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wb_stb <= 1'b0;
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else if (tx_int)
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else if (tx_int)
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// If we aren't at the end of the message, and tx_int
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// tells us the FIFO is empty, then start writing into
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// the FIFO>
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wb_stb <= 1'b1;
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wb_stb <= 1'b1;
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else if (txfifo_int)
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else if (txfifo_int)
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// If we are writing into the FIFO, and it's less than
|
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// half full (i.e. txfifo_int is true) then keep going.
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wb_stb <= wb_stb;
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wb_stb <= wb_stb;
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else
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else
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// But once the FIFO gets to half full, stop.
|
wb_stb <= 1'b0;
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wb_stb <= 1'b0;
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// We aren't using the receive interrupts, so we'll just mark them
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// We aren't using the receive interrupts, so we'll just mark them
|
// here as ignored.
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// here as ignored.
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wire ignored_rx_int, ignored_rxfifo_int;
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wire ignored_rx_int, ignored_rxfifo_int;
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// Finally--the unit under test--now that we've set up all the wires
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// Finally--the unit under test--now that we've set up all the wires
|
// to run/test it.
|
// to run/test it.
|
wbuart #(30'h868)
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wbuart #(INITIAL_UART_SETUP)
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wbuarti(i_clk, pwr_reset,
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wbuarti(i_clk, pwr_reset,
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wb_stb, wb_stb, 1'b1, wb_addr, wb_data,
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wb_stb, wb_stb, 1'b1, wb_addr, wb_data,
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uart_stall, uart_ack, uart_data,
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uart_stall, uart_ack, uart_data,
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1'b1, o_uart_tx,
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1'b1, o_uart_tx,
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ignored_rx_int, tx_int,
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ignored_rx_int, tx_int,
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