| Line 44... |
Line 44... |
\usepackage{amsmath}
|
\usepackage{amsmath}
|
\project{WBUART32}
|
\project{WBUART32}
|
\title{Specification}
|
\title{Specification}
|
\author{Dan Gisselquist, Ph.D.}
|
\author{Dan Gisselquist, Ph.D.}
|
\email{dgisselq (at) ieee.org}
|
\email{dgisselq (at) ieee.org}
|
\revision{Rev.~0.1}
|
\revision{Rev.~1.0}
|
\begin{document}
|
\begin{document}
|
\pagestyle{gqtekspecplain}
|
\pagestyle{gqtekspecplain}
|
\titlepage
|
\titlepage
|
\begin{license}
|
\begin{license}
|
Copyright (C) 2016--2017, Gisselquist Technology, LLC.
|
Copyright (C) 2016--2017, Gisselquist Technology, LLC.
|
| Line 65... |
Line 65... |
|
|
You should have received a copy of the GNU General Public License along
|
You should have received a copy of the GNU General Public License along
|
with this program. If not, see \texttt{http://www.gnu.org/licenses/} for a copy.
|
with this program. If not, see \texttt{http://www.gnu.org/licenses/} for a copy.
|
\end{license}
|
\end{license}
|
\begin{revisionhistory}
|
\begin{revisionhistory}
|
|
1.0 & 2/20/2017 & D. Gisselquist & Added Hardware Flow Control\\\hline
|
0.2 & 1/03/2017 & D. Gisselquist & Added test-bench information\\\hline
|
0.2 & 1/03/2017 & D. Gisselquist & Added test-bench information\\\hline
|
0.1 & 8/26/2016 & D. Gisselquist & Initial Draft Specification\\\hline
|
0.1 & 8/26/2016 & D. Gisselquist & Initial Draft Specification\\\hline
|
\end{revisionhistory}
|
\end{revisionhistory}
|
% Revision History
|
% Revision History
|
% Table of Contents, named Contents
|
% Table of Contents, named Contents
|
| Line 115... |
Line 116... |
a result, full two-way interaction can be had between a simulation and a
|
a result, full two-way interaction can be had between a simulation and a
|
terminal or other port. Indeed, this may even be sufficient to connect a
|
terminal or other port. Indeed, this may even be sufficient to connect a
|
CPU, capable of running Linux, to a terminal to verify that yes it can truly
|
CPU, capable of running Linux, to a terminal to verify that yes it can truly
|
run Linux--all within Verilator.
|
run Linux--all within Verilator.
|
|
|
As a final addition, there are three files in the test bench section which can
|
As a final addition, there are four files in the test bench section which can
|
be used as top--level design files to prove whether or not the serial port on
|
be used as top--level design files to prove whether or not the serial port on
|
a given circuit board works.
|
a given circuit board works.
|
|
|
\chapter{Architecture}\label{ch:arch}
|
\chapter{Architecture}\label{ch:arch}
|
|
|
The HDL portion of the core itself consists of four basic files: {\tt rxuart.v},
|
The HDL portion of the core itself consists of four basic files: {\tt rxuart.v},
|
{\tt txuart.v}, {\tt ufifo.v} and {\tt wbuart.v}. These are, respectively, the
|
{\tt txuart.v}, {\tt ufifo.v} and {\tt wbuart.v}. These are, respectively, the
|
receive UART code, the transmit UART code, a fairly generic FIFO, and a fully
|
receive UART code, the transmit UART code, a fairly generic FIFO, and a fully
|
wishbone compliant UART peripheral. This latter files demonstrates one example
|
wishbone compliant UART peripheral. This latter file demonstrates one example
|
of how the receiver, transmitter, and FIFOs may be connected to a Wishbone bus.
|
of how the receiver, transmitter, and a pair of FIFOs may be connected to a
|
A fifth file, {\tt wbuart-insert.v}, demonstrates how the {\tt rxuart.v} and
|
Wishbone bus. A fifth file, {\tt wbuart-insert.v}, demonstrates how the
|
{\tt txuart.v} files may be included into a module implementing a simpler
|
{\tt rxuart.v} and {\tt txuart.v} files may be included into a module
|
interface.
|
implementing a simpler wishbone interface without the FIFO.
|
|
|
Each of the core files, {\tt rxuart.v} and {\tt txuart.v}, are fully capable.
|
Each of the core files, {\tt rxuart.v} and {\tt txuart.v}, are fully capable.
|
They each accept a 29--bit setup value specifying baud rate, the number of bits
|
They each accept a 30--bit setup value specifying baud rate, the number of bits
|
per byte (between 5 and 8), whether or not parity is used, whether that parity
|
per byte (between 5 and 8), whether hardware flow control is off, or whether or
|
is even, odd, or fixed mark or fixed space. This setup register will be
|
not parity is used, and if so whether that parity is even, odd, or fixed mark
|
discussed further in Chap.\ref{ch:registers}.
|
or fixed space. This setup register will be discussed further in
|
|
Chap.\ref{ch:registers}.
|
|
|
A further note on the {\tt rxuart.v} module is in order. This module double
|
A further note on the {\tt rxuart.v} module is in order. This module double
|
latches the input, in the proper two buffer fashion to avoid problems with
|
latches the input, in the proper two buffer fashion to avoid problems with
|
metastability. Then, upon the detection of the start bit (i.e. a high to low
|
metastability. Then, upon the detection of the start bit (i.e. a high to low
|
transition), the port waits a half of a baud, and then starts its baud clock
|
transition), the port waits a half of a baud, and then starts its baud clock
|
| Line 162... |
Line 164... |
$f_{\mbox{\tiny SYS}}$, the number of data rates that can actually be
|
$f_{\mbox{\tiny SYS}}$, the number of data rates that can actually be
|
synthesized becomes limited.
|
synthesized becomes limited.
|
|
|
Connecting to either {\tt txuart.v} or {\tt rxuart.v} is quite simple. Both
|
Connecting to either {\tt txuart.v} or {\tt rxuart.v} is quite simple. Both
|
files have a data port and a strobe. To transmit, set the data and strobe
|
files have a data port and a strobe. To transmit, set the data and strobe
|
lines. Drop the strobe line as soon as the strobe is asserted and the busy line
|
lines. Drop the strobe line on the clock after the busy line was low.
|
is not.
|
|
Likewise, to connect to the {\tt rxuart.v} port, there is a data
|
Likewise, to connect to the {\tt rxuart.v} port, there is a data
|
and a strobe. This time, though, these two wires are outputs of the receive
|
and a strobe. This time, though, these two wires are outputs of the receive
|
module as opposed to inputs.
|
module as opposed to inputs.
|
When the strobe is high, the data is valid. It will only be high for one
|
When the strobe is high, the data is valid. It will only be high for one
|
clock period. If you wish to connect this output to a bus, a register will be
|
clock period. If you wish to connect this output to a bus, a register will be
|
needed to hold the strobe high until the data is read. Also, while the strobe
|
needed to hold the strobe high until the data is read, as in
|
|
{\tt wbuart-insert.v}. Also, while the strobe
|
is high, the {\tt o\_frame\_err} will indicate whether or not there was a
|
is high, the {\tt o\_frame\_err} will indicate whether or not there was a
|
framing error (i.e., no stop bit), and {\tt o\_parity\_err} will indicate
|
framing error (i.e., no stop bit), and {\tt o\_parity\_err} will indicate
|
whether or not the parity matched. Finally, the {\tt o\_break} line will
|
whether or not the parity matched. Finally, the {\tt o\_break} line will
|
indicate whether the receiver is in a ``break'' state,
|
indicate whether the receiver is in a ``break'' state,
|
|
|
| Line 185... |
Line 187... |
An simple example of how to put this configuration together is found in
|
An simple example of how to put this configuration together is found in
|
{\tt wbuart-insert.v}. In this example given, the {\tt rx\_data} register
|
{\tt wbuart-insert.v}. In this example given, the {\tt rx\_data} register
|
will have only the lower eight bits set if the data is valid, higher bits will
|
will have only the lower eight bits set if the data is valid, higher bits will
|
be set upon error conditions, and cleared automatically upon the next byte read.
|
be set upon error conditions, and cleared automatically upon the next byte read.
|
In a similar fashion, the {\tt tx\_data} register can be written to with a byte
|
In a similar fashion, the {\tt tx\_data} register can be written to with a byte
|
in order to transmit that byte. Writing bit nine will place the transmitter
|
in order to transmit that byte. Writing bit ten will place the transmitter
|
into a ``break'' condition, only cleared by writing a zero to that bit later.
|
into a ``break'' condition, which will only be cleared by writing a zero to
|
|
that bit later.
|
Reading from the {\tt tx\_data} register can also be used to determine if the
|
Reading from the {\tt tx\_data} register can also be used to determine if the
|
transmitter is busy (via polling), whether it is currently in a break condition,
|
transmitter is busy (via polling), whether it is currently in a break condition,
|
or even what bit is currently being placed to the output port.
|
or even what bit is currently being placed to the output port.
|
|
|
A more comprehensive example of how these UART modules may be used together
|
A more comprehensive example of how these UART modules may be used together
|
| Line 211... |
Line 214... |
Finally, there are a series of example files found in the bench/verilog
|
Finally, there are a series of example files found in the bench/verilog
|
directory. {\tt helloworld.v} presents an example of a simple UART transmitter
|
directory. {\tt helloworld.v} presents an example of a simple UART transmitter
|
sending the ``Hello, World {\textbackslash}r{\textbackslash}n'' message over
|
sending the ``Hello, World {\textbackslash}r{\textbackslash}n'' message over
|
and over again. This example
|
and over again. This example
|
uses only the {\tt txuart.v} module, and can be simulated in Verilator.
|
uses only the {\tt txuart.v} module, and can be simulated in Verilator.
|
A second test file, {\tt linetest.v}, works by waiting for a line of data to be
|
A second test file, {\tt echotest.v}, works by echoing every received character
|
received, after which it parrots that line back to the terminal. This tests
|
to the transmit port.
|
both {\tt txuart.v} and {\tt rxuart.v}. A third test file, {\tt speechfifo.v}
|
This tests both {\tt txuart.v} and {\tt rxuart.v}.
|
tests both the wishbone interface as well as the FIFO, by filling the UART,
|
A third test file, {\tt linetest.v}, works by waiting for a line of data to be
|
10~samples at a time, with text from Abraham Lincoln's Gettysburg address.
|
received, after which it parrots that line back to the terminal.
|
All three of these files have an internal option to define
|
A fourth test file, {\tt speechfifo.v} tests both the wishbone interface as
|
{\tt OPT\_STANDALONE}. If and when defined, they may be used as top--level
|
well as the FIFO, by filling the UART, 10~samples at a time, with text from
|
files as part of a UART test.
|
Abraham Lincoln's Gettysburg address.
|
|
All three of these example files may be used as stand-alone top--level design
|
|
files to verify your own UART hardware functionality.
|
|
|
\chapter{Operation}\label{ch:ops}
|
\chapter{Operation}\label{ch:ops}
|
|
|
% This section describes the operation of the core. Specific sequences, such
|
% This section describes the operation of the core. Specific sequences, such
|
% as startup sequences, as well as the modes and states of the block should be
|
% as startup sequences, as well as the modes and states of the block should be
|
% described.
|
% described.
|
%
|
%
|
|
|
To use the core, a couple of steps are required. First, wire it up. The
|
To use the core, a couple of steps are required. First, wire it up. This
|
|
includes wiring the {\tt i\_uart} and {\tt o\_uart} ports, as well as any
|
|
{\tt i\_rts} and/or {\tt o\_cts} hardware flow control. The
|
{\tt rxuart.v} and {\tt txuart.v} files may be wired up for use individually,
|
{\tt rxuart.v} and {\tt txuart.v} files may be wired up for use individually,
|
or using an example such as {\tt wbuart-insert.v}. Alternatively, the
|
or as part of a large module such as the example in{\tt wbuart-insert.v}.
|
{\tt wbuart.v} file may be connected to a straight 32--bit wishbone bus.
|
Alternatively, the {\tt wbuart.v} file may be connected to a straight 32--bit
|
|
wishbone bus.
|
Second, set the UART configuration register. This is ideally set by setting
|
Second, set the UART configuration register. This is ideally set by setting
|
the {\tt INITIAL\_SETUP} parameter of {\tt rxuart}, {\tt txuart} or even
|
the {\tt INITIAL\_SETUP} parameter of {\tt rxuart}, {\tt txuart} or even
|
{\tt wbuart.v} Alternatively, you can write to the setup register at a later
|
{\tt wbuart} Alternatively, you can write to the setup register at a later
|
time, as is done with the {\tt speechfifo.v} bench test.
|
time, as is done within the {\tt speechfifo.v} bench test.
|
|
|
From a simulation standpoint, it will also need to be ``wired'' up in your
|
From a simulation standpoint, it will also need to be ``wired'' up inside your
|
C++ main Verilator file. Somewhere, internal to the top--level Verilator
|
C++ main Verilator file. Somewhere, internal to the top--level Verilator
|
C++ simulation file, you'll want to have some setup lines similar to,
|
C++ simulation file, you'll want to have some setup lines similar to,
|
\begin{tabbing}
|
\begin{tabbing}
|
\hbox to 3.0in{\tt \#include "uartsim.h"} \= {\em // Tell compiler about UARTSIM}\\
|
\hbox to 3.0in{\tt \#include "uartsim.h"} \= {\em // Tell compiler about UARTSIM}\\
|
\vdots \\
|
\vdots \\
|
| Line 316... |
Line 324... |
The setup register is perhaps the most critical of all the registers. This
|
The setup register is perhaps the most critical of all the registers. This
|
is shown in Fig.\ref{fig:SETUP}.
|
is shown in Fig.\ref{fig:SETUP}.
|
\begin{figure}\begin{center}
|
\begin{figure}\begin{center}
|
\begin{bytefield}[endianness=big]{32}
|
\begin{bytefield}[endianness=big]{32}
|
\bitheader{0-31}\\
|
\bitheader{0-31}\\
|
\bitbox{2}{00}
|
\bitbox{1}{0}
|
|
\bitbox{1}{H}
|
\bitbox{2}{N}
|
\bitbox{2}{N}
|
\bitbox{1}{S}
|
\bitbox{1}{S}
|
\bitbox{1}{P}
|
\bitbox{1}{P}
|
\bitbox{1}{F}
|
\bitbox{1}{F}
|
\bitbox{1}{T}
|
\bitbox{1}{T}
|
\bitbox{24}{Baud CLKS}
|
\bitbox{24}{Baud CLKS}
|
\end{bytefield}
|
\end{bytefield}
|
\caption{SETUP Register fields}\label{fig:SETUP}
|
\caption{SETUP Register fields}\label{fig:SETUP}
|
\end{center}\end{figure}
|
\end{center}\end{figure}
|
It is designed so that, for any 8N1 protocol (eight data bits, no parity, one
|
It is designed so that, for any 8N1 protocol (eight data bits, no parity, one
|
stop bit), all of the upper bits will be set to zero so that only the number of
|
stop bit, hardware flow control on), all of the upper bits will be set to zero
|
clocks per baud interval needs to be set. The top two bits are unused, making
|
so that only the number of
|
this a 30--bit number.\footnote{The top two bits are ideally suited for adding
|
clocks per baud interval needs to be set.
|
in a user configurable hardware flow control: one for flow control in use, zero
|
The top bit is unused, making this a 31--bit number.
|
otherwise, but this is only a future upgrade possibility as of this writing.}
|
The other fields are: $H$ which, when set, turns off any hardware flow
|
The other fields are: $N$ sets the number of bits per word. A value of zero
|
control. $N$ sets the number of bits per word. A value of zero
|
corresponds to 8--bit words, a value of one to seven bit words, and so forth up
|
corresponds to 8--bit words, a value of one to seven bit words, and so forth up
|
to a value of three for five bit words. $S$ determines the number of stop
|
to a value of three for five bit words. $S$ determines the number of stop
|
bits. Set this to one for two stop bits, or leave it at zero for a single
|
bits. Set this to one for two stop bits, or leave it at zero for a single
|
stop bit. $P$ determines whether or not a parity bit is used (1~for parity,
|
stop bit. $P$ determines whether or not a parity bit is used (1~for parity,
|
0~for no parity), while $F$ determines whether or not the parity is fixed.
|
0~for no parity), while $F$ determines whether or not the parity is fixed.
|
| Line 351... |
Line 360... |
0 & & & No parity \\\hline
|
0 & & & No parity \\\hline
|
\end{tabular}\caption{Parity setup}\label{tbl:parity}
|
\end{tabular}\caption{Parity setup}\label{tbl:parity}
|
\end{center}\end{table}
|
\end{center}\end{table}
|
|
|
The final portion of this register is the baud {\tt CLKS}. This is the number
|
The final portion of this register is the baud {\tt CLKS}. This is the number
|
of ticks of your ssytem clock per baud interval,
|
of ticks of your system clock per baud interval,
|
\begin{eqnarray*}
|
\begin{eqnarray*}
|
{\tt CLKS} &=& \frac{f_{\mbox{\tiny SYS}}}{f_{\mbox{\tiny BAUD}}}.
|
{\tt CLKS} &=& \frac{f_{\mbox{\tiny SYS}}}{f_{\mbox{\tiny BAUD}}}.
|
\end{eqnarray*}
|
\end{eqnarray*}
|
Rounding to the nearest integer is recommended. Hence, if you have a system
|
Rounding to the nearest integer is recommended. Hence, if you have a system
|
clock of 100~MHz and wish to achieve 115,200~Baud, you would set {\tt CLKS} to
|
clock of 100~MHz and wish to achieve 115,200~Baud, you would set {\tt CLKS} to
|
| Line 403... |
Line 412... |
\end{center}\end{figure}
|
\end{center}\end{figure}
|
We'll discuss each of these bits individually.
|
We'll discuss each of these bits individually.
|
|
|
The {\tt LGLN} field indicates the log base two of the FIFO length. Hence an
|
The {\tt LGLN} field indicates the log base two of the FIFO length. Hence an
|
{\tt LGLN} field of four would indicate a FIFO length of sixteen values.
|
{\tt LGLN} field of four would indicate a FIFO length of sixteen values.
|
The FIFO fill indicates the current level of fill. The $H$ bit will be true
|
The FIFO fill for the transmitter indicates the number of available spaces
|
if the FIFO is half full, and the $Z$ bit will be true if the FIFO is non-empty.
|
within the transmit FIFO, while the FIFO fill in the receiver indicates the
|
|
current number of spaces within the FIFO having valid data. The $H$ bit will
|
|
be true if the high order FIFO fill bit is set.
|
|
Finally, the $Z$ bit will be true for the transmitter if there is at least one
|
|
open space in the FIFO, and true in the receiver if there is at least one value
|
|
needing to be read.
|
|
|
The $H$ and $Z$ bits also mirror the interrupt bits generated by {\tt wbuart.v}.
|
The $H$ and $Z$ bits also mirror the interrupt bits generated by {\tt wbuart.v}.
|
Interrupts will be generated any time the FIFO is half full (on receive), or
|
Interrupts will be generated any time the FIFO is half full (on receive), or
|
less than half full (on transmit). The same logic applies for the $Z$ bit.
|
less than half full (on transmit). The same logic applies for the $Z$ bit. An
|
|
interrupt will be generated any time the FIFO in non-empty (on receive), or
|
|
not full (on transmit).
|
|
|
Writes to this register are quietly ignored.
|
Writes to this FIFO status register are quietly ignored.
|
|
|
\section{RX\_DATA Register}
|
\section{RX\_DATA Register}
|
Fig.~\ref{fig:RXDATA}
|
Fig.~\ref{fig:RXDATA}
|
\begin{figure}\begin{center}
|
\begin{figure}\begin{center}
|
\begin{bytefield}[endianness=big]{32}
|
\begin{bytefield}[endianness=big]{32}
|
| Line 444... |
Line 460... |
be false when the {\tt RWORD} is valid. Hence, if {\tt (RWORD \& ~0x0ff)} is
|
be false when the {\tt RWORD} is valid. Hence, if {\tt (RWORD \& ~0x0ff)} is
|
zero there is a word ready to be received without error.
|
zero there is a word ready to be received without error.
|
|
|
The $E$ bit is an error bit. When set, it indicates that the FIFO has
|
The $E$ bit is an error bit. When set, it indicates that the FIFO has
|
overflowed sometime since the last reset. This bit is also a reset bit.
|
overflowed sometime since the last reset. This bit is also a reset bit.
|
In other words, writing a {\tt 1'b0} to this bit will command a receive
|
In other words, writing a {\tt 1'b1} to this bit will command a receive
|
reset: clearing the FIFO, and waiting for the line to be idle before receiving
|
reset: clearing the FIFO, and waiting for the line to be idle before receiving
|
another byte. This bit is not implemented in {\tt wbuart-insert.v}, but
|
another byte. This bit is not implemented in {\tt wbuart-insert.v}, but
|
exists in the {\tt wbuart.v} implementation.
|
exists in the {\tt wbuart.v} implementation.
|
|
|
\section{TX\_DATA Register}
|
\section{TX\_DATA Register}
|
Fig.~\ref{fig:TXDATA}
|
Fig.~\ref{fig:TXDATA}
|
\begin{figure}\begin{center}
|
\begin{figure}\begin{center}
|
\begin{bytefield}[endianness=big]{32}
|
\begin{bytefield}[endianness=big]{32}
|
\bitheader{0-31}\\
|
\bitheader{0-31}\\
|
\bitbox[lrt]{17}{17'h00}
|
\bitbox[lrt]{16}{16'h00}
|
|
\bitbox{1}{R}
|
\bitbox{1}{H}
|
\bitbox{1}{H}
|
\bitbox{1}{Z}
|
\bitbox{1}{Z}
|
\bitbox{1}{E}
|
\bitbox{1}{E}
|
\bitbox[lrt]{1}{C}
|
\bitbox[lrt]{1}{C}
|
\bitbox[lrt]{1}{O}
|
\bitbox[lrt]{1}{O}
|
| Line 479... |
Line 496... |
{\tt wbuart.v}. The $C$ field indicates whether or not the receive
|
{\tt wbuart.v}. The $C$ field indicates whether or not the receive
|
data line is high or low, the $O$ field indicates the same for the transmit
|
data line is high or low, the $O$ field indicates the same for the transmit
|
line. These aren't particularly useful or valuable, but the $C$ bit doesn't
|
line. These aren't particularly useful or valuable, but the $C$ bit doesn't
|
fit in the receive data register since it would violate the error condition
|
fit in the receive data register since it would violate the error condition
|
detector. These two bits are thrown in here for whatever useful purpose one
|
detector. These two bits are thrown in here for whatever useful purpose one
|
might find. The $B$ field, when set, sends a break condition down the wire.
|
might find. The $B$ field, when set, transmits a break condition.
|
Further, writes to the TXDATA register while in a break condition and with the
|
Further, writes to the TXDATA register while in a break condition and with the
|
$B$ field clear, will clear the transmitter from any break condition without
|
$B$ field clear, will clear the transmitter from any break condition without
|
transmitting anything. The $S$ field is similar to the RXDATA strobe register.
|
transmitting anything. The $S$ field is similar to the RXDATA strobe register.
|
It is a read--only bit that will be true any time the transmitter is busy.
|
It is a read--only bit that will be true any time the transmitter is busy.
|
It will be clear only when the transmitter is idle.
|
It will be clear only when the transmitter is idle.
|
|
Finally, the upper $R$ bit at the top of the register is the instantaneous
|
|
value of the received ready-to-send (RTS) value.
|
|
|
The final three bits, $H$, $Z$, and $E$, are present only in {\tt wbuart.v}.
|
The final three bits, $H$, $Z$, and $E$, are present only in {\tt wbuart.v}.
|
These bits indicate $H$ if the FIFO is at least half full, $Z$ if the FIFO is
|
These bits indicate $H$ if the FIFO is at least half full, $Z$ if the FIFO is
|
empty, and $E$ if the FIFO has experienced an overflow condition since the
|
not full, and $E$ if the FIFO has experienced an overflow condition since the
|
last reset. Writing a {\tt 1'b1} to the $E$ bit will reset the transmit FIFO,
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last reset. Writing a {\tt 1'b1} to the $E$ bit will reset the transmit FIFO,
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both clearing any error indication in the FIFO as well as clearing the FIFO
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both clearing any error indication in the FIFO as well as clearing the FIFO
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itself.
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itself.
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|
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To use the transmitter, simply write a byte to the TXDATA register
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To use the transmitter, simply write a byte to the TXDATA register
|
| Line 550... |
Line 569... |
is required by the wishbone specification in order to declare the core as
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is required by the wishbone specification in order to declare the core as
|
wishbone compliant, and so it is included here. It references the connections
|
wishbone compliant, and so it is included here. It references the connections
|
used in {\tt wbuart.v} as well as those exemplified by {\tt wbuart-insert.v}.
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used in {\tt wbuart.v} as well as those exemplified by {\tt wbuart-insert.v}.
|
The big thing to notice is that this core acts as a wishbone slave, and that
|
The big thing to notice is that this core acts as a wishbone slave, and that
|
all accesses to the core registers are 32--bit reads and writes to this
|
all accesses to the core registers are 32--bit reads and writes to this
|
interface---not the 8--bit reads or writes that might otherwise be expected.
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interface---not the 8--bit reads or writes that might be expected from any
|
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other 8'bit serial interface.
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|
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What this table doesn't show is that all accesses to the port take a single
|
What this table doesn't show is that all accesses to the port take a single
|
clock for {\tt wbuart-insert.v}, or two clocks for {\tt wbuart.v}. That is, if
|
clock for {\tt wbuart-insert.v}, or two clocks for {\tt wbuart.v}. That is, if
|
the {\tt i\_wb\_stb} line is high on one clock, the {\tt i\_wb\_ack} line will
|
the {\tt i\_wb\_stb} line is high on one clock, the {\tt i\_wb\_ack} line will
|
be high the next for single clock access, or the clock after that for two
|
be high the next for single clock access, or the clock after that for two
|
| Line 576... |
Line 596... |
\begin{tabbing}
|
\begin{tabbing}
|
{\tt if (!clk)} \= \\
|
{\tt if (!clk)} \= \\
|
\> {\tt tb->i\_uart\_rx} {\tt = } {\tt uartsim(tb->o\_uart\_tx);}
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\> {\tt tb->i\_uart\_rx} {\tt = } {\tt uartsim(tb->o\_uart\_tx);}
|
\end{tabbing}
|
\end{tabbing}
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|
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For those interested in hardware flow control, the core also offers an
|
|
{\tt i\_rts} input to control the flow out of our transmitter, and an
|
|
{\tt o\_cts} output when the receiver is full.
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|
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A more detailed discussion of the connections associated with these modules
|
A more detailed discussion of the connections associated with these modules
|
can begin with Tbl.~\ref{tbl:rxports},
|
can begin with Tbl.~\ref{tbl:rxports},
|
\begin{table}\begin{center}\begin{portlist}
|
\begin{table}\begin{center}\begin{portlist}
|
{\tt i\_clk} & 1 & Input & The system clock \\\hline
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{\tt i\_clk} & 1 & Input & The system clock \\\hline
|
{\tt i\_reset} & 1 & Input & A positive, synchronous reset \\\hline
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{\tt i\_reset} & 1 & Input & A positive, synchronous reset \\\hline
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{\tt i\_setup} & 30 & Input & The 30--bit setup register \\\hline
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{\tt i\_setup} & 31 & Input & The 31--bit setup register \\\hline
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{\tt i\_uart} & 1 & Input & The input wire from the outside world. \\\hline
|
{\tt i\_uart} & 1 & Input & The input wire from the outside world. \\\hline
|
{\tt o\_wr} & 1 & Output & True if a word was received. At this time,
|
{\tt o\_wr} & 1 & Output & True if a word was received. At this time,
|
{\tt o\_data}, {\tt o\_break}, {\tt o\_parity\_err}, and
|
{\tt o\_data}, {\tt o\_break}, {\tt o\_parity\_err}, and
|
{\tt o\_frame\_err} will also be valid. \\\hline
|
{\tt o\_frame\_err} will also be valid. \\\hline
|
{\tt o\_data} & 8 & Output & The received data, valid if {\tt o\_wr} \\\hline
|
{\tt o\_data} & 8 & Output & The received data, valid if {\tt o\_wr} \\\hline
|
| Line 597... |
Line 621... |
\end{center}\end{table}
|
\end{center}\end{table}
|
detailing the I/O ports of the UART receiver, Tbl.~\ref{tbl:txports},
|
detailing the I/O ports of the UART receiver, Tbl.~\ref{tbl:txports},
|
\begin{table}\begin{center}\begin{portlist}
|
\begin{table}\begin{center}\begin{portlist}
|
{\tt i\_clk} & 1 & Input & The system clock \\\hline
|
{\tt i\_clk} & 1 & Input & The system clock \\\hline
|
{\tt i\_reset} & 1 & Input & A positive, synchronous reset \\\hline
|
{\tt i\_reset} & 1 & Input & A positive, synchronous reset \\\hline
|
{\tt i\_setup} & 30 & Input & The 30--bit setup register \\\hline
|
{\tt i\_setup} & 31 & Input & The 31--bit setup register \\\hline
|
{\tt i\_break} & 1 & Input & Set to true to place the transmit channel into a break condition\\\hline
|
{\tt i\_break} & 1 & Input & Set to true to place the transmit channel into a break condition\\\hline
|
{\tt i\_wr} & 1 & Input & An input strobe. Set to one when you wish to transmit data, clear once it has been accepted\\\hline
|
{\tt i\_wr} & 1 & Input & An input strobe. Set to one when you wish to transmit data, clear once it has been accepted\\\hline
|
{\tt i\_data} & 8 & Input & The data to be transmitted, ignored unless
|
{\tt i\_data} & 8 & Input & The data to be transmitted, ignored unless
|
{\tt (i\_wr)\&\&(!o\_busy)} \\\hline
|
{\tt (i\_wr)\&\&(!o\_busy)} \\\hline
|
|
{\tt i\_rts} & 1 & Input & A hardware flow control wire, true if the receiver is ready to receive\\\hline
|
{\tt o\_uart} & 1 & Output & The wire to be connected to the external port\\\hline
|
{\tt o\_uart} & 1 & Output & The wire to be connected to the external port\\\hline
|
{\tt o\_busy} & 1 & Output & True if the transmitter is busy, false if it will receive data\\\hline
|
{\tt o\_busy} & 1 & Output & True if the transmitter is busy, false if it will receive data\\\hline
|
\end{portlist}\caption{TXUART port list}\label{tbl:txports}
|
\end{portlist}\caption{TXUART port list}\label{tbl:txports}
|
\end{center}\end{table}
|
\end{center}\end{table}
|
detailing the I/O ports of the UART transmitter, and Tbl.~\ref{tbl:wbports}
|
detailing the I/O ports of the UART transmitter, and Tbl.~\ref{tbl:wbports}
|
\begin{table}\begin{center}\begin{tabular}{|p{1.15in}|p{0.1in}|p{0.75in}|p{3.375in}|}
|
\begin{table}\begin{center}\begin{tabular}{|p{1.15in}|p{0.1in}|p{0.75in}|p{3.375in}|}
|
\rowcolor[gray]{0.85} Port & W & Direction & Description \\\hline\hline
|
\rowcolor[gray]{0.85} Port & W & Direction & Description \\\hline\hline
|
{\tt i\_uart\_rx}& 1 & Input & The receive wire coming from the external port\\\hline
|
{\tt i\_uart\_rx}& 1 & Input & The receive wire coming from the external port\\\hline
|
{\tt o\_uart\_tx}& 1 & Output & The transmit wire to be connected to the external port\\\hline
|
{\tt o\_uart\_tx}& 1 & Output & The transmit wire to be connected to the external port\\\hline
|
|
{\tt i\_rts}& 1 & Input & The hardware flow control {\tt ready-to-send} (i.e. receive) input for the transmitter\\\hline
|
|
{\tt o\_cts}& 1 & Output & The hardware flow control {\tt clear-to-send} output\\\hline
|
{\tt o\_uart\_rx\_int} & 1 & Output & True if a byte may be read from the receiver\\\hline
|
{\tt o\_uart\_rx\_int} & 1 & Output & True if a byte may be read from the receiver\\\hline
|
{\tt o\_uart\_tx\_int} & 1 & Output & True if the transmitter is idle\\\hline
|
{\tt o\_uart\_tx\_int} & 1 & Output & True if a byte may be sent to the transmitter\\\hline
|
{\tt o\_uart\_rxfifo\_int}&1& Output & True if the receive FIFO is half full\\\hline
|
{\tt o\_uart\_rxfifo\_int}&1& Output & True if the receive FIFO is half full\\\hline
|
{\tt o\_uart\_txfifo\_int}&1& Output & True if the transmit FIFO is half empty\\\hline
|
{\tt o\_uart\_txfifo\_int}&1& Output & True if the transmit FIFO is half empty\\\hline
|
\end{tabular}\caption{WBUART port list}\label{tbl:wbports}
|
\end{tabular}\caption{WBUART port list}\label{tbl:wbports}
|
\end{center}\end{table}
|
\end{center}\end{table}
|
detailing the non--wishbone I/O ports of the wishbone controller.
|
detailing the non--wishbone I/O ports of the wishbone controller.
|
