| Line 208... |
Line 208... |
simulator is as simple as calculating the receive input bit from the transmit
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simulator is as simple as calculating the receive input bit from the transmit
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output bit when the clock is low, and the core takes care of everything else.
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output bit when the clock is low, and the core takes care of everything else.
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Finally, there are a series of example files found in the bench/verilog
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Finally, there are a series of example files found in the bench/verilog
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directory. {\tt helloworld.v} presents an example of a simple UART transmitter
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directory. {\tt helloworld.v} presents an example of a simple UART transmitter
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sending the ``Hello, World \\r\\n'' message over and over again. This example
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sending the ``Hello, World {\textbackslash}r{\textbackslash}n'' message over
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and over again. This example
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uses only the {\tt txuart.v} module, and can be simulated in Verilator.
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uses only the {\tt txuart.v} module, and can be simulated in Verilator.
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A second test file, {\tt linetest.v}, works by waiting for a line of data to be
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A second test file, {\tt linetest.v}, works by waiting for a line of data to be
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received, after which it parrots that line back to the terminal. This tests
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received, after which it parrots that line back to the terminal. This tests
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both {\tt txuart.v} and {\tt rxuart.v}. A third test file, {\tt speechfifo.v}
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both {\tt txuart.v} and {\tt rxuart.v}. A third test file, {\tt speechfifo.v}
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tests both the wishbone interface as well as the FIFO, by filling the UART,
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tests both the wishbone interface as well as the FIFO, by filling the UART,
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| Line 349... |
Line 350... |
1 & 1 & 1 & Parity bit is a Mark (1'b1)\\\hline
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1 & 1 & 1 & Parity bit is a Mark (1'b1)\\\hline
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0 & & & No parity \\\hline
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0 & & & No parity \\\hline
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\end{tabular}\caption{Parity setup}\label{tbl:parity}
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\end{tabular}\caption{Parity setup}\label{tbl:parity}
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\end{center}\end{table}
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\end{center}\end{table}
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The final portion of this register is the baud {\tt CLKS}. This is the number
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of ticks of your ssytem clock per baud interval,
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\begin{eqnarray*}
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{\tt CLKS} &=& \frac{f_{\mbox{\tiny SYS}}}{f_{\mbox{\tiny BAUD}}}.
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\end{eqnarray*}
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Rounding to the nearest integer is recommended. Hence, if you have a system
|
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clock of 100~MHz and wish to achieve 115,200~Baud, you would set {\tt CLKS} to
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\begin{eqnarray*}
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{\tt CLKS}_{\tiny{\tt Example}} &=& \frac{100 \cdot 10^6}{115200}
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\frac{\mbox{Clocks per Second}}{\mbox{Baud Intervals per Second}}
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\approx 868 \mbox{ Clocks per Baud Interval}
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\end{eqnarray*}
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Changes to this setup register will take place in the transmitter as soon as
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Changes to this setup register will take place in the transmitter as soon as
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the transmitter is idle and ready to accept another byte.
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the transmitter is idle and ready to accept another byte.
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Changes to this setup register in {\tt rxuart.v} also take place between bytes.
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Changes to this setup register in {\tt rxuart.v} also take place between bytes.
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However, within the {\tt wbuart.v} context, any changes to the setup register
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However, within the {\tt wbuart.v} context, any changes to the setup register
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