OpenCores
URL https://opencores.org/ocsvn/wbuart32/wbuart32/trunk

Subversion Repositories wbuart32

[/] [wbuart32/] [trunk/] [rtl/] [rxuart.v] - Diff between revs 9 and 14

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 9 Rev 14
Line 17... Line 17...
//      There is a synchronous reset line, logic high.
//      There is a synchronous reset line, logic high.
//
//
//      Now for the setup register.  The register is 32 bits, so that this
//      Now for the setup register.  The register is 32 bits, so that this
//      UART may be set up over a 32-bit bus.
//      UART may be set up over a 32-bit bus.
//
//
//      i_setup[30]     True if we are using hardware flow control.  This bit
//      i_setup[30]     True if we are not using hardware flow control.  This bit
//              is ignored within this module, as any receive hardware flow
//              is ignored within this module, as any receive hardware flow
//              control will need to be implemented elsewhere.
//              control will need to be implemented elsewhere.
//
//
//      i_setup[29:28]  Indicates the number of data bits per word.  This will
//      i_setup[29:28]  Indicates the number of data bits per word.  This will
//              either be 2'b00 for an 8-bit word, 2'b01 for a 7-bit word, 2'b10
//              either be 2'b00 for an 8-bit word, 2'b01 for a 7-bit word, 2'b10

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.