URL https://opencores.org/ocsvn/wbuart32/wbuart32/trunk

Subversion Repositories wbuart32

[/] [wbuart32/] [trunk/] [rtl/] [rxuart.v] - Diff between revs 14 and 17

Rev 14	Rev 17
Line 87...	Line 87...
`//`	`//`
`//`	`//`
`////////////////////////////////////////////////////////////////////////////////`	`////////////////////////////////////////////////////////////////////////////////`
`//`	`//`
`//`	`//`
	`default_nettype none
	`//`
`// States: (@ baud counter == 0)`	`// States: (@ baud counter == 0)`
`// 0 First bit arrives`	`// 0 First bit arrives`
`// ..7 Bits arrive`	`// ..7 Bits arrive`
`// 8 Stop bit (x1)`	`// 8 Stop bit (x1)`
`// 9 Stop bit (x2)`	`// 9 Stop bit (x2)`
Line 117...	Line 119...

`module rxuart(i_clk, i_reset, i_setup, i_uart_rx, o_wr, o_data, o_break,`	`module rxuart(i_clk, i_reset, i_setup, i_uart_rx, o_wr, o_data, o_break,`
`o_parity_err, o_frame_err, o_ck_uart);`	`o_parity_err, o_frame_err, o_ck_uart);`
`parameter [30:0] INITIAL_SETUP = 31'd868;`	`parameter [30:0] INITIAL_SETUP = 31'd868;`
`// 8 data bits, no parity, (at least 1) stop bit`	`// 8 data bits, no parity, (at least 1) stop bit`
`input i_clk, i_reset;`	`input wire i_clk, i_reset;`
`input [30:0] i_setup;`	`input wire [30:0] i_setup;`
`input i_uart_rx;`	`input wire i_uart_rx;`
`output reg o_wr;`	`output reg o_wr;`
`output reg [7:0] o_data;`	`output reg [7:0] o_data;`
`output reg o_break;`	`output reg o_break;`
`output reg o_parity_err, o_frame_err;`	`output reg o_parity_err, o_frame_err;`
`output wire o_ck_uart;`	`output wire o_ck_uart;`