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https://opencores.org/ocsvn/wbuart32/wbuart32/trunk
[/] [wbuart32/] [trunk/] [rtl/] [rxuart.v] - Diff between revs 5 and 7
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| Rev 5 |
Rev 7 |
| Line 127... |
Line 127... |
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wire [27:0] clocks_per_baud, break_condition, half_baud;
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wire [27:0] clocks_per_baud, break_condition, half_baud;
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wire [1:0] data_bits;
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wire [1:0] data_bits;
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wire use_parity, parity_even, dblstop, fixd_parity;
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wire use_parity, parity_even, dblstop, fixd_parity;
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reg [29:0] r_setup;
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reg [29:0] r_setup;
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reg [3:0] state;
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assign clocks_per_baud = { 4'h0, r_setup[23:0] };
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assign clocks_per_baud = { 4'h0, r_setup[23:0] };
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assign data_bits = r_setup[29:28];
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assign data_bits = r_setup[29:28];
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assign dblstop = r_setup[27];
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assign dblstop = r_setup[27];
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assign use_parity = r_setup[26];
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assign use_parity = r_setup[26];
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Line 244... |
// use_parity
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// use_parity
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// dblstop
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// dblstop
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// Logic outputs (4):
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// Logic outputs (4):
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// state
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// state
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//
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//
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reg [3:0] state;
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initial state = `RXU_RESET_IDLE;
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initial state = `RXU_RESET_IDLE;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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if (i_reset)
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if (i_reset)
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state <= `RXU_RESET_IDLE;
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state <= `RXU_RESET_IDLE;
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