| Line 17... |
Line 17... |
// There is a synchronous reset line, logic high.
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// There is a synchronous reset line, logic high.
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//
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//
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// Now for the setup register. The register is 32 bits, so that this
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// Now for the setup register. The register is 32 bits, so that this
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// UART may be set up over a 32-bit bus.
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// UART may be set up over a 32-bit bus.
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//
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//
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// i_setup[30] True if we are using hardware flow control. This bit
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// is ignored within this module, as any receive hardware flow
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// control will need to be implemented elsewhere.
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//
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// i_setup[29:28] Indicates the number of data bits per word. This will
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// i_setup[29:28] Indicates the number of data bits per word. This will
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// either be 2'b00 for an 8-bit word, 2'b01 for a 7-bit word, 2'b10
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// either be 2'b00 for an 8-bit word, 2'b01 for a 7-bit word, 2'b10
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// for a six bit word, or 2'b11 for a five bit word.
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// for a six bit word, or 2'b11 for a five bit word.
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//
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//
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// i_setup[27] Indicates whether or not to use one or two stop bits.
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// i_setup[27] Indicates whether or not to use one or two stop bits.
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| Line 72... |
Line 76... |
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// You should have received a copy of the GNU General Public License along
|
// You should have received a copy of the GNU General Public License along
|
// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// with this program. (It's in the $(ROOT)/doc directory. Run make with no
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// target there if the PDF file isn't present.) If not, see
|
// target there if the PDF file isn't present.) If not, see
|
// <http://www.gnu.org/licenses/> for a copy.
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// <http://www.gnu.org/licenses/> for a copy.
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//
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//
|
// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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| Line 88... |
Line 92... |
// States: (@ baud counter == 0)
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// States: (@ baud counter == 0)
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// 0 First bit arrives
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// 0 First bit arrives
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// ..7 Bits arrive
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// ..7 Bits arrive
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// 8 Stop bit (x1)
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// 8 Stop bit (x1)
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// 9 Stop bit (x2)
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// 9 Stop bit (x2)
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/// c break condition
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// c break condition
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// d Waiting for the channel to go high
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// d Waiting for the channel to go high
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// e Waiting for the reset to complete
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// e Waiting for the reset to complete
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// f Idle state
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// f Idle state
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`define RXU_BIT_ZERO 4'h0
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`define RXU_BIT_ZERO 4'h0
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`define RXU_BIT_ONE 4'h1
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`define RXU_BIT_ONE 4'h1
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| Line 111... |
Line 115... |
`define RXU_RESET_IDLE 4'he
|
`define RXU_RESET_IDLE 4'he
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`define RXU_IDLE 4'hf
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`define RXU_IDLE 4'hf
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|
|
module rxuart(i_clk, i_reset, i_setup, i_uart_rx, o_wr, o_data, o_break,
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module rxuart(i_clk, i_reset, i_setup, i_uart_rx, o_wr, o_data, o_break,
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o_parity_err, o_frame_err, o_ck_uart);
|
o_parity_err, o_frame_err, o_ck_uart);
|
parameter INITIAL_SETUP = 30'd868;
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parameter [30:0] INITIAL_SETUP = 31'd868;
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// 8 data bits, no parity, (at least 1) stop bit
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// 8 data bits, no parity, (at least 1) stop bit
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input i_clk, i_reset;
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input i_clk, i_reset;
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input [29:0] i_setup;
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input [30:0] i_setup;
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input i_uart_rx;
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input i_uart_rx;
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output reg o_wr;
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output reg o_wr;
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output reg [7:0] o_data;
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output reg [7:0] o_data;
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output reg o_break;
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output reg o_break;
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output reg o_parity_err, o_frame_err;
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output reg o_parity_err, o_frame_err;
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| Line 130... |
Line 134... |
wire use_parity, parity_even, dblstop, fixd_parity;
|
wire use_parity, parity_even, dblstop, fixd_parity;
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reg [29:0] r_setup;
|
reg [29:0] r_setup;
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reg [3:0] state;
|
reg [3:0] state;
|
|
|
assign clocks_per_baud = { 4'h0, r_setup[23:0] };
|
assign clocks_per_baud = { 4'h0, r_setup[23:0] };
|
|
// assign hw_flow_control = !r_setup[30];
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assign data_bits = r_setup[29:28];
|
assign data_bits = r_setup[29:28];
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assign dblstop = r_setup[27];
|
assign dblstop = r_setup[27];
|
assign use_parity = r_setup[26];
|
assign use_parity = r_setup[26];
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assign fixd_parity = r_setup[25];
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assign fixd_parity = r_setup[25];
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assign parity_even = r_setup[24];
|
assign parity_even = r_setup[24];
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| Line 212... |
Line 217... |
half_baud_time <= (~ck_uart)&&(chg_counter >= half_baud);
|
half_baud_time <= (~ck_uart)&&(chg_counter >= half_baud);
|
|
|
|
|
// Allow our controlling processor to change our setup at any time
|
// Allow our controlling processor to change our setup at any time
|
// outside of receiving/processing a character.
|
// outside of receiving/processing a character.
|
initial r_setup = INITIAL_SETUP;
|
initial r_setup = INITIAL_SETUP[29:0];
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (state >= `RXU_RESET_IDLE)
|
if (state >= `RXU_RESET_IDLE)
|
r_setup <= i_setup;
|
r_setup <= i_setup[29:0];
|
|
|
|
|
// Our monster state machine. YIKES!
|
// Our monster state machine. YIKES!
|
//
|
//
|
// Yeah, this may be more complicated than it needs to be. The basic
|
// Yeah, this may be more complicated than it needs to be. The basic
|
