| Line 19... |
Line 19... |
// Creator: Dan Gisselquist, Ph.D.
|
// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
|
//
|
////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
//
|
//
|
// Copyright (C) 2015-2017, Gisselquist Technology, LLC
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// Copyright (C) 2015-2018, Gisselquist Technology, LLC
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//
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//
|
// This program is free software (firmware): you can redistribute it and/or
|
// This program is free software (firmware): you can redistribute it and/or
|
// modify it under the terms of the GNU General Public License as published
|
// modify it under the terms of the GNU General Public License as published
|
// by the Free Software Foundation, either version 3 of the License, or (at
|
// by the Free Software Foundation, either version 3 of the License, or (at
|
// your option) any later version.
|
// your option) any later version.
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| Line 54... |
Line 54... |
`define RXUL_BIT_FOUR 4'h4
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`define RXUL_BIT_FOUR 4'h4
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`define RXUL_BIT_FIVE 4'h5
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`define RXUL_BIT_FIVE 4'h5
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`define RXUL_BIT_SIX 4'h6
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`define RXUL_BIT_SIX 4'h6
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`define RXUL_BIT_SEVEN 4'h7
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`define RXUL_BIT_SEVEN 4'h7
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`define RXUL_STOP 4'h8
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`define RXUL_STOP 4'h8
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`define RXUL_WAIT 4'h9
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`define RXUL_IDLE 4'hf
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`define RXUL_IDLE 4'hf
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|
|
module rxuartlite(i_clk, i_uart_rx, o_wr, o_data);
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module rxuartlite(i_clk, i_uart_rx, o_wr, o_data);
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parameter [23:0] CLOCKS_PER_BAUD = 24'd868;
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parameter TIMER_BITS = 10;
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parameter [(TIMER_BITS-1):0] CLOCKS_PER_BAUD = 868; // 115200 MBaud at 100MHz
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|
localparam TB = TIMER_BITS;
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input wire i_clk;
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input wire i_clk;
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input wire i_uart_rx;
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input wire i_uart_rx;
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output reg o_wr;
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output reg o_wr;
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output reg [7:0] o_data;
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output reg [7:0] o_data;
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|
|
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wire [23:0] half_baud;
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wire [(TB-1):0] half_baud;
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reg [3:0] state;
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reg [3:0] state;
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|
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assign half_baud = { 1'b0, CLOCKS_PER_BAUD[23:1] } - 24'h1;
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assign half_baud = { 1'b0, CLOCKS_PER_BAUD[(TB-1):1] };
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reg [23:0] baud_counter;
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reg [(TB-1):0] baud_counter;
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reg zero_baud_counter;
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reg zero_baud_counter;
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|
|
|
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// Since this is an asynchronous receiver, we need to register our
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// Since this is an asynchronous receiver, we need to register our
|
// input a couple of clocks over to avoid any problems with
|
// input a couple of clocks over to avoid any problems with
|
// metastability. We do that here, and then ignore all but the
|
// metastability. We do that here, and then ignore all but the
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// ck_uart wire.
|
// ck_uart wire.
|
reg q_uart, qq_uart, ck_uart;
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reg q_uart, qq_uart, ck_uart;
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initial q_uart = 1'b0;
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initial q_uart = 1'b1;
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initial qq_uart = 1'b0;
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initial qq_uart = 1'b1;
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initial ck_uart = 1'b0;
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initial ck_uart = 1'b1;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
|
{ ck_uart, qq_uart, q_uart } <= { qq_uart, q_uart, i_uart_rx };
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q_uart <= i_uart_rx;
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qq_uart <= q_uart;
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ck_uart <= qq_uart;
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end
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|
|
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// Keep track of the number of clocks since the last change.
|
// Keep track of the number of clocks since the last change.
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//
|
//
|
// This is used to determine if we are in either a break or an idle
|
// This is used to determine if we are in either a break or an idle
|
// condition, as discussed further below.
|
// condition, as discussed further below.
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reg [23:0] chg_counter;
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reg [(TB-1):0] chg_counter;
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initial chg_counter = 24'h00;
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initial chg_counter = {(TB){1'b1}};
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always @(posedge i_clk)
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always @(posedge i_clk)
|
if (qq_uart != ck_uart)
|
if (qq_uart != ck_uart)
|
chg_counter <= 24'h00;
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chg_counter <= 0;
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else
|
else if (chg_counter != { (TB){1'b1} })
|
chg_counter <= chg_counter + 1;
|
chg_counter <= chg_counter + 1;
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|
|
// Are we in the middle of a baud iterval? Specifically, are we
|
// Are we in the middle of a baud iterval? Specifically, are we
|
// in the middle of a start bit? Set this to high if so. We'll use
|
// in the middle of a start bit? Set this to high if so. We'll use
|
// this within our state machine to transition out of the IDLE
|
// this within our state machine to transition out of the IDLE
|
// state.
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// state.
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reg half_baud_time;
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reg half_baud_time;
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initial half_baud_time = 0;
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initial half_baud_time = 0;
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always @(posedge i_clk)
|
always @(posedge i_clk)
|
half_baud_time <= (~ck_uart)&&(chg_counter >= half_baud);
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half_baud_time <= (!ck_uart)&&(chg_counter >= half_baud-1'b1-1'b1);
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|
|
|
|
initial state = `RXUL_IDLE;
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initial state = `RXUL_IDLE;
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always @(posedge i_clk)
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always @(posedge i_clk)
|
begin
|
begin
|
if (state == `RXUL_IDLE)
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if (state == `RXUL_IDLE)
|
begin // Idle state, independent of baud counter
|
begin // Idle state, independent of baud counter
|
// By default, just stay in the IDLE state
|
// By default, just stay in the IDLE state
|
state <= `RXUL_IDLE;
|
state <= `RXUL_IDLE;
|
if ((~ck_uart)&&(half_baud_time))
|
if ((!ck_uart)&&(half_baud_time))
|
// UNLESS: We are in the center of a valid
|
// UNLESS: We are in the center of a valid
|
// start bit
|
// start bit
|
state <= `RXUL_BIT_ZERO;
|
state <= `RXUL_BIT_ZERO;
|
end else if (zero_baud_counter)
|
end else if ((state >= `RXUL_WAIT)&&(ck_uart))
|
|
state <= `RXUL_IDLE;
|
|
else if (zero_baud_counter)
|
begin
|
begin
|
if (state < `RXUL_STOP)
|
if (state <= `RXUL_STOP)
|
// Data arrives least significant bit first.
|
// Data arrives least significant bit first.
|
// By the time this is clocked in, it's what
|
// By the time this is clocked in, it's what
|
// you'll have.
|
// you'll have.
|
state <= state + 1;
|
state <= state + 1;
|
else // Wait for the next character
|
|
state <= `RXUL_IDLE;
|
|
end
|
end
|
end
|
end
|
|
|
// Data bit capture logic.
|
// Data bit capture logic.
|
//
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//
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| Line 140... |
Line 139... |
// upon: 1) it doesn't matter what it is until the end of a captured
|
// upon: 1) it doesn't matter what it is until the end of a captured
|
// byte, and 2) the data register will flush itself of any invalid
|
// byte, and 2) the data register will flush itself of any invalid
|
// data in all other cases. Hence, let's keep it real simple.
|
// data in all other cases. Hence, let's keep it real simple.
|
reg [7:0] data_reg;
|
reg [7:0] data_reg;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (zero_baud_counter)
|
if ((zero_baud_counter)&&(state != `RXUL_STOP))
|
data_reg <= { ck_uart, data_reg[7:1] };
|
data_reg <= { qq_uart, data_reg[7:1] };
|
|
|
// Our data bit logic doesn't need nearly the complexity of all that
|
// Our data bit logic doesn't need nearly the complexity of all that
|
// work above. Indeed, we only need to know if we are at the end of
|
// work above. Indeed, we only need to know if we are at the end of
|
// a stop bit, in which case we copy the data_reg into our output
|
// a stop bit, in which case we copy the data_reg into our output
|
// data register, o_data, and tell others (for one clock) that data is
|
// data register, o_data, and tell others (for one clock) that data is
|
// available.
|
// available.
|
//
|
//
|
|
initial o_wr = 1'b0;
|
initial o_data = 8'h00;
|
initial o_data = 8'h00;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((zero_baud_counter)&&(state == `RXUL_STOP))
|
if ((zero_baud_counter)&&(state == `RXUL_STOP)&&(ck_uart))
|
begin
|
begin
|
o_wr <= 1'b1;
|
o_wr <= 1'b1;
|
o_data <= data_reg;
|
o_data <= data_reg;
|
end else
|
end else
|
o_wr <= 1'b0;
|
o_wr <= 1'b0;
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| Line 164... |
Line 164... |
//
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//
|
// This is used as a "clock divider" if you will, but the clock needs
|
// This is used as a "clock divider" if you will, but the clock needs
|
// to be reset before any byte can be decoded. In all other respects,
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// to be reset before any byte can be decoded. In all other respects,
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// we set ourselves up for CLOCKS_PER_BAUD counts between baud
|
// we set ourselves up for CLOCKS_PER_BAUD counts between baud
|
// intervals.
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// intervals.
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initial baud_counter = 0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((zero_baud_counter)|||(state == `RXUL_IDLE))
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if (((state==`RXUL_IDLE))&&(!ck_uart)&&(half_baud_time))
|
baud_counter <= CLOCKS_PER_BAUD-1'b1;
|
baud_counter <= CLOCKS_PER_BAUD-1'b1;
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else
|
else if (state == `RXUL_WAIT)
|
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baud_counter <= 0;
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else if ((zero_baud_counter)&&(state < `RXUL_STOP))
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baud_counter <= CLOCKS_PER_BAUD-1'b1;
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else if (!zero_baud_counter)
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baud_counter <= baud_counter-1'b1;
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baud_counter <= baud_counter-1'b1;
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|
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// zero_baud_counter
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// zero_baud_counter
|
//
|
//
|
// Rather than testing whether or not (baud_counter == 0) within our
|
// Rather than testing whether or not (baud_counter == 0) within our
|
// (already too complicated) state transition tables, we use
|
// (already too complicated) state transition tables, we use
|
// zero_baud_counter to pre-charge that test on the clock
|
// zero_baud_counter to pre-charge that test on the clock
|
// before--cleaning up some otherwise difficult timing dependencies.
|
// before--cleaning up some otherwise difficult timing dependencies.
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initial zero_baud_counter = 1'b0;
|
initial zero_baud_counter = 1'b1;
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always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (state == `RXUL_IDLE)
|
if ((state == `RXUL_IDLE)&&(!ck_uart)&&(half_baud_time))
|
zero_baud_counter <= 1'b0;
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zero_baud_counter <= 1'b0;
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else if (state == `RXUL_WAIT)
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zero_baud_counter <= 1'b1;
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else if ((zero_baud_counter)&&(state < `RXUL_STOP))
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|
zero_baud_counter <= 1'b0;
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else if (baud_counter == 1)
|
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zero_baud_counter <= 1'b1;
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|
|
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`ifdef FORMAL
|
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`define FORMAL_VERILATOR
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`else
|
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`ifdef VERILATOR
|
|
`define FORMAL_VERILATOR
|
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`endif
|
|
`endif
|
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|
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`ifdef FORMAL
|
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|
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// `define PHASE_TWO // SymbiYosys controls this definition
|
|
`define PHASE_ONE_ASSERT assert
|
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`define PHASE_TWO_ASSERT assert
|
|
|
|
`ifdef PHASE_TWO
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|
`undef PHASE_ONE_ASSERT
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`define PHASE_ONE_ASSERT assume
|
|
`endif
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|
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localparam F_CKRES = 10;
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|
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wire f_tx_start, f_tx_busy;
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wire [(F_CKRES-1):0] f_tx_step;
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|
reg f_tx_zclk;
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reg [(TB-1):0] f_tx_timer;
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wire [7:0] f_rx_newdata;
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reg [(TB-1):0] f_tx_baud;
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wire f_tx_zbaud;
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|
|
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wire [(TB-1):0] f_max_baud_difference;
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reg [(TB-1):0] f_baud_difference;
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reg [(TB+3):0] f_tx_count, f_rx_count;
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|
wire [7:0] f_tx_data;
|
|
|
|
|
|
|
|
wire f_txclk;
|
|
reg [1:0] f_rx_clock;
|
|
reg [(F_CKRES-1):0] f_tx_clock;
|
|
reg f_past_valid, f_past_valid_tx;
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|
|
|
initial f_past_valid = 1'b0;
|
|
always @(posedge i_clk)
|
|
f_past_valid <= 1'b1;
|
|
|
|
initial f_rx_clock = 3'h0;
|
|
always @($global_clock)
|
|
f_rx_clock <= f_rx_clock + 1'b1;
|
|
|
|
always @(*)
|
|
assume(i_clk == f_rx_clock[1]);
|
|
|
|
|
|
|
|
///////////////////////////////////////////////////////////
|
|
//
|
|
//
|
|
// Generate a transmitted signal
|
|
//
|
|
//
|
|
///////////////////////////////////////////////////////////
|
|
|
|
|
|
// First, calculate the transmit clock
|
|
localparam [(F_CKRES-1):0] F_MIDSTEP = { 2'b01, {(F_CKRES-2){1'b0}} };
|
|
//
|
|
// Need to allow us to slip by half a baud clock over 10 baud intervals
|
|
//
|
|
// (F_STEP / (2^F_CKRES)) * (CLOCKS_PER_BAUD)*10 < CLOCKS_PER_BAUD/2
|
|
// F_STEP * 2 * 10 < 2^F_CKRES
|
|
localparam [(F_CKRES-1):0] F_HALFSTEP= F_MIDSTEP/32;
|
|
localparam [(F_CKRES-1):0] F_MINSTEP = F_MIDSTEP - F_HALFSTEP + 1;
|
|
localparam [(F_CKRES-1):0] F_MAXSTEP = F_MIDSTEP + F_HALFSTEP - 1;
|
|
|
|
initial assert(F_MINSTEP <= F_MIDSTEP);
|
|
initial assert(F_MIDSTEP <= F_MAXSTEP);
|
|
|
|
assign f_tx_step = $anyconst;
|
|
// assume((f_tx_step >= F_MINSTEP)&&(f_tx_step <= F_MAXSTEP));
|
|
//
|
|
//
|
|
always @(*) assume((f_tx_step == F_MINSTEP)
|
|
||(f_tx_step == F_MIDSTEP)
|
|
||(f_tx_step == F_MAXSTEP));
|
|
|
|
// initial rx_clock = $anyseq;
|
|
always @($global_clock)
|
|
f_tx_clock <= f_tx_clock + f_tx_step;
|
|
|
|
assign f_txclk = f_tx_clock[F_CKRES-1];
|
|
|
|
//
|
|
initial f_past_valid_tx = 1'b0;
|
|
always @(posedge f_txclk)
|
|
f_past_valid_tx <= 1'b1;
|
|
|
|
initial assume(i_uart_rx);
|
|
|
|
|
|
//////////////////////////////////////////////
|
|
//
|
|
//
|
|
// Build a simulated transmitter
|
|
//
|
|
//
|
|
//////////////////////////////////////////////
|
|
//
|
|
// First, the simulated timing generator
|
|
|
|
// parameter TIMER_BITS = 10;
|
|
// parameter [(TIMER_BITS-1):0] CLOCKS_PER_BAUD = 868;
|
|
// localparam TB = TIMER_BITS;
|
|
|
|
assign f_tx_start = $anyseq;
|
|
always @(*)
|
|
if (f_tx_busy)
|
|
assume(!f_tx_start);
|
|
|
|
initial f_tx_baud = 0;
|
|
always @(posedge f_txclk)
|
|
if ((f_tx_zbaud)&&((f_tx_busy)||(f_tx_start)))
|
|
f_tx_baud <= CLOCKS_PER_BAUD-1'b1;
|
|
else if (!f_tx_zbaud)
|
|
f_tx_baud <= f_tx_baud - 1'b1;
|
|
|
|
always @(*)
|
|
`PHASE_ONE_ASSERT(f_tx_baud < CLOCKS_PER_BAUD);
|
|
|
|
always @(*)
|
|
if (!f_tx_busy)
|
|
`PHASE_ONE_ASSERT(f_tx_baud == 0);
|
|
|
|
assign f_tx_zbaud = (f_tx_baud == 0);
|
|
|
|
// Pick some data to transmit
|
|
assign f_tx_data = $anyseq;
|
|
|
|
// But only if we aren't busy
|
|
initial assume(f_tx_data == 0);
|
|
always @(posedge f_txclk)
|
|
if ((!f_tx_zbaud)||(f_tx_busy)||(!f_tx_start))
|
|
assume(f_tx_data == $past(f_tx_data));
|
|
|
|
// Force the data to change on a clock only
|
|
always @($global_clock)
|
|
if ((f_past_valid)&&(!$rose(f_txclk)))
|
|
assume($stable(f_tx_data));
|
|
else if (f_tx_busy)
|
|
assume($stable(f_tx_data));
|
|
|
|
//
|
|
always @($global_clock)
|
|
if ((!f_past_valid)||(!$rose(f_txclk)))
|
|
begin
|
|
assume($stable(f_tx_start));
|
|
assume($stable(f_tx_data));
|
|
end
|
|
|
|
//
|
|
//
|
|
//
|
|
|
|
reg [9:0] f_tx_reg;
|
|
reg f_tx_busy;
|
|
|
|
// Here's the transmitter itself (roughly)
|
|
initial f_tx_busy = 1'b0;
|
|
initial f_tx_reg = 0;
|
|
always @(posedge f_txclk)
|
|
if (!f_tx_zbaud)
|
|
begin
|
|
`PHASE_ONE_ASSERT(f_tx_busy);
|
|
end else begin
|
|
f_tx_reg <= { 1'b0, f_tx_reg[9:1] };
|
|
if (f_tx_start)
|
|
f_tx_reg <= { 1'b1, f_tx_data, 1'b0 };
|
|
end
|
|
|
|
// Create a busy flag that we'll use
|
|
always @(*)
|
|
if (!f_tx_zbaud)
|
|
f_tx_busy <= 1'b1;
|
|
else if (|f_tx_reg)
|
|
f_tx_busy <= 1'b1;
|
|
else
|
|
f_tx_busy <= 1'b0;
|
|
|
|
//
|
|
// Tie the TX register to the TX data
|
|
always @(posedge f_txclk)
|
|
if (f_tx_reg[9])
|
|
`PHASE_ONE_ASSERT(f_tx_reg[8:0] == { f_tx_data, 1'b0 });
|
|
else if (f_tx_reg[8])
|
|
`PHASE_ONE_ASSERT(f_tx_reg[7:0] == f_tx_data[7:0] );
|
|
else if (f_tx_reg[7])
|
|
`PHASE_ONE_ASSERT(f_tx_reg[6:0] == f_tx_data[7:1] );
|
|
else if (f_tx_reg[6])
|
|
`PHASE_ONE_ASSERT(f_tx_reg[5:0] == f_tx_data[7:2] );
|
|
else if (f_tx_reg[5])
|
|
`PHASE_ONE_ASSERT(f_tx_reg[4:0] == f_tx_data[7:3] );
|
|
else if (f_tx_reg[4])
|
|
`PHASE_ONE_ASSERT(f_tx_reg[3:0] == f_tx_data[7:4] );
|
|
else if (f_tx_reg[3])
|
|
`PHASE_ONE_ASSERT(f_tx_reg[2:0] == f_tx_data[7:5] );
|
|
else if (f_tx_reg[2])
|
|
`PHASE_ONE_ASSERT(f_tx_reg[1:0] == f_tx_data[7:6] );
|
|
else if (f_tx_reg[1])
|
|
`PHASE_ONE_ASSERT(f_tx_reg[0] == f_tx_data[7]);
|
|
|
|
// Our counter since we start
|
|
initial f_tx_count = 0;
|
|
always @(posedge f_txclk)
|
|
if (!f_tx_busy)
|
|
f_tx_count <= 0;
|
|
else
|
|
f_tx_count <= f_tx_count + 1'b1;
|
|
|
|
always @(*)
|
|
if (f_tx_reg == 10'h0)
|
|
assume(i_uart_rx);
|
|
else
|
|
assume(i_uart_rx == f_tx_reg[0]);
|
|
|
|
//
|
|
// Make sure the absolute transmit clock timer matches our state
|
|
//
|
|
always @(posedge f_txclk)
|
|
if (!f_tx_busy)
|
|
begin
|
|
if ((!f_past_valid_tx)||(!$past(f_tx_busy)))
|
|
`PHASE_ONE_ASSERT(f_tx_count == 0);
|
|
end else if (f_tx_reg[9])
|
|
`PHASE_ONE_ASSERT(f_tx_count ==
|
|
CLOCKS_PER_BAUD -1 -f_tx_baud);
|
|
else if (f_tx_reg[8])
|
|
`PHASE_ONE_ASSERT(f_tx_count ==
|
|
2 * CLOCKS_PER_BAUD -1 -f_tx_baud);
|
|
else if (f_tx_reg[7])
|
|
`PHASE_ONE_ASSERT(f_tx_count ==
|
|
3 * CLOCKS_PER_BAUD -1 -f_tx_baud);
|
|
else if (f_tx_reg[6])
|
|
`PHASE_ONE_ASSERT(f_tx_count ==
|
|
4 * CLOCKS_PER_BAUD -1 -f_tx_baud);
|
|
else if (f_tx_reg[5])
|
|
`PHASE_ONE_ASSERT(f_tx_count ==
|
|
5 * CLOCKS_PER_BAUD -1 -f_tx_baud);
|
|
else if (f_tx_reg[4])
|
|
`PHASE_ONE_ASSERT(f_tx_count ==
|
|
6 * CLOCKS_PER_BAUD -1 -f_tx_baud);
|
|
else if (f_tx_reg[3])
|
|
`PHASE_ONE_ASSERT(f_tx_count ==
|
|
7 * CLOCKS_PER_BAUD -1 -f_tx_baud);
|
|
else if (f_tx_reg[2])
|
|
`PHASE_ONE_ASSERT(f_tx_count ==
|
|
8 * CLOCKS_PER_BAUD -1 -f_tx_baud);
|
|
else if (f_tx_reg[1])
|
|
`PHASE_ONE_ASSERT(f_tx_count ==
|
|
9 * CLOCKS_PER_BAUD -1 -f_tx_baud);
|
|
else if (f_tx_reg[0])
|
|
`PHASE_ONE_ASSERT(f_tx_count ==
|
|
10 * CLOCKS_PER_BAUD -1 -f_tx_baud);
|
|
else
|
|
`PHASE_ONE_ASSERT(f_tx_count ==
|
|
11 * CLOCKS_PER_BAUD -1 -f_tx_baud);
|
|
|
|
|
|
///////////////////////////////////////
|
|
//
|
|
// Receiver
|
|
//
|
|
///////////////////////////////////////
|
|
//
|
|
// Count RX clocks since the start of the first stop bit, measured in
|
|
// rx clocks
|
|
initial f_rx_count = 0;
|
|
always @(posedge i_clk)
|
|
if (state == `RXUL_IDLE)
|
|
f_rx_count = (!ck_uart) ? (chg_counter+2) : 0;
|
|
else
|
|
f_rx_count <= f_rx_count + 1'b1;
|
|
always @(posedge i_clk)
|
|
if (state == 0)
|
|
`PHASE_ONE_ASSERT(f_rx_count
|
|
== half_baud + (CLOCKS_PER_BAUD-baud_counter));
|
|
else if (state == 1)
|
|
`PHASE_ONE_ASSERT(f_rx_count == half_baud + 2 * CLOCKS_PER_BAUD
|
|
- baud_counter);
|
|
else if (state == 2)
|
|
`PHASE_ONE_ASSERT(f_rx_count == half_baud + 3 * CLOCKS_PER_BAUD
|
|
- baud_counter);
|
|
else if (state == 3)
|
|
`PHASE_ONE_ASSERT(f_rx_count == half_baud + 4 * CLOCKS_PER_BAUD
|
|
- baud_counter);
|
|
else if (state == 4)
|
|
`PHASE_ONE_ASSERT(f_rx_count == half_baud + 5 * CLOCKS_PER_BAUD
|
|
- baud_counter);
|
|
else if (state == 5)
|
|
`PHASE_ONE_ASSERT(f_rx_count == half_baud + 6 * CLOCKS_PER_BAUD
|
|
- baud_counter);
|
|
else if (state == 6)
|
|
`PHASE_ONE_ASSERT(f_rx_count == half_baud + 7 * CLOCKS_PER_BAUD
|
|
- baud_counter);
|
|
else if (state == 7)
|
|
`PHASE_ONE_ASSERT(f_rx_count == half_baud + 8 * CLOCKS_PER_BAUD
|
|
- baud_counter);
|
|
else if (state == 8)
|
|
`PHASE_ONE_ASSERT((f_rx_count == half_baud + 9 * CLOCKS_PER_BAUD
|
|
- baud_counter)
|
|
||(f_rx_count == half_baud + 10 * CLOCKS_PER_BAUD
|
|
- baud_counter));
|
|
|
|
always @(*)
|
|
`PHASE_ONE_ASSERT( ((!zero_baud_counter)
|
|
&&(state == `RXUL_IDLE)
|
|
&&(baud_counter == 0))
|
|
||((zero_baud_counter)&&(baud_counter == 0))
|
|
||((!zero_baud_counter)&&(baud_counter != 0)));
|
|
|
|
always @(posedge i_clk)
|
|
if (!f_past_valid)
|
|
`PHASE_ONE_ASSERT((state == `RXUL_IDLE)&&(baud_counter == 0)
|
|
&&(zero_baud_counter));
|
|
|
|
always @(*)
|
|
begin
|
|
`PHASE_ONE_ASSERT({ ck_uart,qq_uart,q_uart,i_uart_rx } != 4'h2);
|
|
`PHASE_ONE_ASSERT({ ck_uart,qq_uart,q_uart,i_uart_rx } != 4'h4);
|
|
`PHASE_ONE_ASSERT({ ck_uart,qq_uart,q_uart,i_uart_rx } != 4'h5);
|
|
`PHASE_ONE_ASSERT({ ck_uart,qq_uart,q_uart,i_uart_rx } != 4'h6);
|
|
`PHASE_ONE_ASSERT({ ck_uart,qq_uart,q_uart,i_uart_rx } != 4'h9);
|
|
`PHASE_ONE_ASSERT({ ck_uart,qq_uart,q_uart,i_uart_rx } != 4'ha);
|
|
`PHASE_ONE_ASSERT({ ck_uart,qq_uart,q_uart,i_uart_rx } != 4'hb);
|
|
`PHASE_ONE_ASSERT({ ck_uart,qq_uart,q_uart,i_uart_rx } != 4'hd);
|
|
end
|
|
|
|
always @(posedge i_clk)
|
|
if ((f_past_valid)&&($past(state) >= `RXUL_WAIT)&&($past(ck_uart)))
|
|
`PHASE_ONE_ASSERT(state == `RXUL_IDLE);
|
|
|
|
always @(posedge i_clk)
|
|
if ((f_past_valid)&&($past(state) >= `RXUL_WAIT)
|
|
&&(($past(state) != `RXUL_IDLE)||(state == `RXUL_IDLE)))
|
|
`PHASE_ONE_ASSERT(zero_baud_counter);
|
|
|
|
// Calculate an absolute value of the difference between the two baud
|
|
// clocks
|
|
`ifdef PHASE_TWO
|
|
always @(posedge i_clk)
|
|
if ((f_past_valid)&&($past(state)==`RXUL_IDLE)&&(state == `RXUL_IDLE))
|
|
begin
|
|
`PHASE_TWO_ASSERT(($past(ck_uart))
|
|
||(chg_counter <=
|
|
{ 1'b0, CLOCKS_PER_BAUD[(TB-1):1] }));
|
|
end
|
|
|
|
always @(posedge f_txclk)
|
|
if (!f_past_valid_tx)
|
|
`PHASE_TWO_ASSERT((state == `RXUL_IDLE)&&(baud_counter == 0)
|
|
&&(zero_baud_counter)&&(!f_tx_busy));
|
|
|
|
wire [(TB+3):0] f_tx_count_two_clocks_ago;
|
|
assign f_tx_count_two_clocks_ago = f_tx_count - 2;
|
|
always @(*)
|
|
if (f_tx_count >= f_rx_count + 2)
|
|
f_baud_difference = f_tx_count_two_clocks_ago - f_rx_count;
|
|
else
|
|
f_baud_difference = f_rx_count - f_tx_count_two_clocks_ago;
|
|
|
|
localparam F_SYNC_DLY = 8;
|
|
|
|
wire [(TB+4+F_CKRES-1):0] f_sub_baud_difference;
|
|
reg [F_CKRES-1:0] ck_tx_clock;
|
|
reg [((F_SYNC_DLY-1)*F_CKRES)-1:0] q_tx_clock;
|
|
reg [TB+3:0] ck_tx_count;
|
|
reg [(F_SYNC_DLY-1)*(TB+4)-1:0] q_tx_count;
|
|
initial q_tx_count = 0;
|
|
initial ck_tx_count = 0;
|
|
initial q_tx_clock = 0;
|
|
initial ck_tx_clock = 0;
|
|
always @($global_clock)
|
|
{ ck_tx_clock, q_tx_clock } <= { q_tx_clock, f_tx_clock };
|
|
always @($global_clock)
|
|
{ ck_tx_count, q_tx_count } <= { q_tx_count, f_tx_count };
|
|
|
|
|
|
wire [TB+4+F_CKRES-1:0] f_ck_tx_time, f_rx_time;
|
|
always @(*)
|
|
f_ck_tx_time = { ck_tx_count, !ck_tx_clock[F_CKRES-1],
|
|
ck_tx_clock[F_CKRES-2:0] };
|
|
always @(*)
|
|
f_rx_time = { f_rx_count, !f_rx_clock[1], f_rx_clock[0],
|
|
{(F_CKRES-2){1'b0}} };
|
|
|
|
wire [TB+4+F_CKRES-1:0] f_signed_difference;
|
|
always @(*)
|
|
f_signed_difference = f_ck_tx_time - f_rx_time;
|
|
|
|
always @(*)
|
|
if (f_signed_difference[TB+4+F_CKRES-1])
|
|
f_sub_baud_difference = -f_signed_difference;
|
|
else
|
|
f_sub_baud_difference = f_signed_difference;
|
|
|
|
always @($global_clock)
|
|
if (state == `RXUL_WAIT)
|
|
`PHASE_TWO_ASSERT((!f_tx_busy)||(f_tx_reg[9:1] == 0));
|
|
|
|
always @($global_clock)
|
|
if (state == `RXUL_IDLE)
|
|
begin
|
|
`PHASE_TWO_ASSERT((!f_tx_busy)||(f_tx_reg[9])||(f_tx_reg[9:1]==0));
|
|
if (!ck_uart)
|
|
;//`PHASE_TWO_ASSERT((f_rx_count < 4)||(f_sub_baud_difference <= ((CLOCKS_PER_BAUD<<F_CKRES)/20)));
|
else
|
else
|
zero_baud_counter <= (baud_counter == 24'h01);
|
`PHASE_TWO_ASSERT((f_tx_reg[9:1]==0)||(f_tx_count < (3 + CLOCKS_PER_BAUD/2)));
|
|
end else if (state == 0)
|
|
`PHASE_TWO_ASSERT(f_sub_baud_difference
|
|
<= 2 * ((CLOCKS_PER_BAUD<<F_CKRES)/20));
|
|
else if (state == 1)
|
|
`PHASE_TWO_ASSERT(f_sub_baud_difference
|
|
<= 3 * ((CLOCKS_PER_BAUD<<F_CKRES)/20));
|
|
else if (state == 2)
|
|
`PHASE_TWO_ASSERT(f_sub_baud_difference
|
|
<= 4 * ((CLOCKS_PER_BAUD<<F_CKRES)/20));
|
|
else if (state == 3)
|
|
`PHASE_TWO_ASSERT(f_sub_baud_difference
|
|
<= 5 * ((CLOCKS_PER_BAUD<<F_CKRES)/20));
|
|
else if (state == 4)
|
|
`PHASE_TWO_ASSERT(f_sub_baud_difference
|
|
<= 6 * ((CLOCKS_PER_BAUD<<F_CKRES)/20));
|
|
else if (state == 5)
|
|
`PHASE_TWO_ASSERT(f_sub_baud_difference
|
|
<= 7 * ((CLOCKS_PER_BAUD<<F_CKRES)/20));
|
|
else if (state == 6)
|
|
`PHASE_TWO_ASSERT(f_sub_baud_difference
|
|
<= 8 * ((CLOCKS_PER_BAUD<<F_CKRES)/20));
|
|
else if (state == 7)
|
|
`PHASE_TWO_ASSERT(f_sub_baud_difference
|
|
<= 9 * ((CLOCKS_PER_BAUD<<F_CKRES)/20));
|
|
else if (state == 8)
|
|
`PHASE_TWO_ASSERT(f_sub_baud_difference
|
|
<= 10 * ((CLOCKS_PER_BAUD<<F_CKRES)/20));
|
|
|
|
always @(posedge i_clk)
|
|
if (o_wr)
|
|
`PHASE_TWO_ASSERT(o_data == $past(f_tx_data,4));
|
|
|
|
// always @(posedge i_clk)
|
|
// if ((zero_baud_counter)&&(state != 4'hf)&&(CLOCKS_PER_BAUD > 6))
|
|
// assert(i_uart_rx == ck_uart);
|
|
|
|
// Make sure the data register matches
|
|
always @(posedge i_clk)
|
|
// if ((f_past_valid)&&(state != $past(state)))
|
|
begin
|
|
if (state == 4'h0)
|
|
`PHASE_TWO_ASSERT(!data_reg[7]);
|
|
|
|
if (state == 4'h1)
|
|
`PHASE_TWO_ASSERT((data_reg[7]
|
|
== $past(f_tx_data[0]))&&(!data_reg[6]));
|
|
|
|
if (state == 4'h2)
|
|
`PHASE_TWO_ASSERT(data_reg[7:6]
|
|
== $past(f_tx_data[1:0]));
|
|
|
|
if (state == 4'h3)
|
|
`PHASE_TWO_ASSERT(data_reg[7:5] == $past(f_tx_data[2:0]));
|
|
|
|
if (state == 4'h4)
|
|
`PHASE_TWO_ASSERT(data_reg[7:4] == $past(f_tx_data[3:0]));
|
|
|
|
if (state == 4'h5)
|
|
`PHASE_TWO_ASSERT(data_reg[7:3] == $past(f_tx_data[4:0]));
|
|
|
|
if (state == 4'h6)
|
|
`PHASE_TWO_ASSERT(data_reg[7:2] == $past(f_tx_data[5:0]));
|
|
|
|
if (state == 4'h7)
|
|
`PHASE_TWO_ASSERT(data_reg[7:1] == $past(f_tx_data[6:0]));
|
|
|
|
if (state == 4'h8)
|
|
`PHASE_TWO_ASSERT(data_reg[7:0] == $past(f_tx_data[7:0]));
|
|
end
|
|
|
|
always @(posedge i_clk)
|
|
cover(o_wr);
|
|
`endif
|
|
`endif
|
|
`ifdef FORMAL_VERILATOR
|
|
// FORMAL properties which can be tested via Verilator as well as
|
|
// Yosys FORMAL
|
|
always @(*)
|
|
assert((state == 4'hf)||(state <= `RXUL_WAIT));
|
|
always @(*)
|
|
assert(zero_baud_counter == (baud_counter == 0)? 1'b1:1'b0);
|
|
always @(*)
|
|
assert(baud_counter <= CLOCKS_PER_BAUD-1'b1);
|
|
|
|
`endif
|
|
|
endmodule
|
endmodule
|
|
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
