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[/] [wbuart32/] [trunk/] [rtl/] [rxuartlite.v] - Diff between revs 21 and 23

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Rev 21	Rev 23
Line 202...	Line 202...
`endif	`endif
`endif	`endif

`ifdef FORMAL	`ifdef FORMAL

// `define PHASE_TWO // SymbiYosys controls this definition	`define ASSUME assume

`define PHASE_ONE_ASSERT assert	`define PHASE_ONE_ASSERT assert
`define PHASE_TWO_ASSERT assert	`define PHASE_TWO_ASSERT assert

`ifdef PHASE_TWO	`ifdef PHASE_TWO
`undef PHASE_ONE_ASSERT	`undef PHASE_ONE_ASSERT
Line 237...	Line 238...

`initial f_past_valid = 1'b0;`	`initial f_past_valid = 1'b0;`
`always @(posedge i_clk)`	`always @(posedge i_clk)`
`f_past_valid <= 1'b1;`	`f_past_valid <= 1'b1;`

	`ifdef F_OPT_CLK2FFLOGIC
`initial f_rx_clock = 3'h0;`	`initial f_rx_clock = 3'h0;`
`always @($global_clock)`	`always @($global_clock)`
`f_rx_clock <= f_rx_clock + 1'b1;`	`f_rx_clock <= f_rx_clock + 1'b1;`

`always @(*)`	`always @(*)`
`assume(i_clk == f_rx_clock[1]);`	`assume(i_clk == f_rx_clock[1]);`
	`endif



`///////////////////////////////////////////////////////////`	`///////////////////////////////////////////////////////////`
`//`	`//`
Line 269...	Line 272...
`localparam [(F_CKRES-1):0] F_MAXSTEP = F_MIDSTEP + F_HALFSTEP - 1;`	`localparam [(F_CKRES-1):0] F_MAXSTEP = F_MIDSTEP + F_HALFSTEP - 1;`

`initial assert(F_MINSTEP <= F_MIDSTEP);`	`initial assert(F_MINSTEP <= F_MIDSTEP);`
`initial assert(F_MIDSTEP <= F_MAXSTEP);`	`initial assert(F_MIDSTEP <= F_MAXSTEP);`

	`ifdef F_OPT_CLK2FFLOGIC
`assign f_tx_step = $anyconst;`	`assign f_tx_step = $anyconst;`
`// assume((f_tx_step >= F_MINSTEP)&&(f_tx_step <= F_MAXSTEP));`	`// assume((f_tx_step >= F_MINSTEP)&&(f_tx_step <= F_MAXSTEP));`
`//`	`//`
`//`	`//`
`always @(*) assume((f_tx_step == F_MINSTEP)`	`always @(*) assume((f_tx_step == F_MINSTEP)`
Line 282...	Line 286...
`// initial rx_clock = $anyseq;`	`// initial rx_clock = $anyseq;`
`always @($global_clock)`	`always @($global_clock)`
`f_tx_clock <= f_tx_clock + f_tx_step;`	`f_tx_clock <= f_tx_clock + f_tx_step;`

`assign f_txclk = f_tx_clock[F_CKRES-1];`	`assign f_txclk = f_tx_clock[F_CKRES-1];`
	`else
	`assign f_tx_clk = i_clk;`
	`endif
`//`	`//`
`initial f_past_valid_tx = 1'b0;`	`initial f_past_valid_tx = 1'b0;`
`always @(posedge f_txclk)`	`always @(posedge f_txclk)`
`f_past_valid_tx <= 1'b1;`	`f_past_valid_tx <= 1'b1;`

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[/] [wbuart32/] [trunk/] [rtl/] [rxuartlite.v] - Diff between revs 21 and 23