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Line 110... |
`define TXU_BREAK 4'he
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`define TXU_BREAK 4'he
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`define TXU_IDLE 4'hf
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`define TXU_IDLE 4'hf
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//
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//
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//
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//
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module txuart(i_clk, i_reset, i_setup, i_break, i_wr, i_data,
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module txuart(i_clk, i_reset, i_setup, i_break, i_wr, i_data,
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i_rts, o_uart_tx, o_busy);
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i_cts_n, o_uart_tx, o_busy);
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parameter [30:0] INITIAL_SETUP = 31'd868;
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parameter [30:0] INITIAL_SETUP = 31'd868;
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input i_clk, i_reset;
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input i_clk, i_reset;
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input [30:0] i_setup;
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input [30:0] i_setup;
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input i_break;
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input i_break;
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input i_wr;
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input i_wr;
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input [7:0] i_data;
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input [7:0] i_data;
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// Hardware flow control Ready-To-Send bit. Set this to one to use
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// Hardware flow control Ready-To-Send bit. Set this to one to use
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// the core without flow control. (A more appropriate name would be
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// the core without flow control. (A more appropriate name would be
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// the Ready-To-Receive bit ...)
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// the Ready-To-Receive bit ...)
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input i_rts;
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input i_cts_n;
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// And the UART input line itself
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// And the UART input line itself
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output reg o_uart_tx;
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output reg o_uart_tx;
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// A line to tell others when we are ready to accept data. If
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// A line to tell others when we are ready to accept data. If
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// (i_wr)&&(!o_busy) is ever true, then the core has accepted a byte
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// (i_wr)&&(!o_busy) is ever true, then the core has accepted a byte
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// for transmission.
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// for transmission.
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Line 154... |
// First step ... handle any hardware flow control, if so enabled.
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// First step ... handle any hardware flow control, if so enabled.
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//
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//
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// Clock in the flow control data, two clocks to avoid metastability
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// Clock in the flow control data, two clocks to avoid metastability
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// Default to using hardware flow control (uart_setup[30]==0 to use it).
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// Default to using hardware flow control (uart_setup[30]==0 to use it).
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// Set this high order bit off if you do not wish to use it.
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// Set this high order bit off if you do not wish to use it.
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reg q_rts, qq_rts, ck_rts;
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reg q_cts_n, qq_cts_n, ck_cts;
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// While we might wish to give initial values to q_rts and ck_rts,
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// While we might wish to give initial values to q_rts and ck_cts,
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// 1) it's not required since the transmitter starts in a long wait
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// 1) it's not required since the transmitter starts in a long wait
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// state, and 2) doing so will prevent the synthesizer from optimizing
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// state, and 2) doing so will prevent the synthesizer from optimizing
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// this pin in the case it is hard set to 1'b1 external to this
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// this pin in the case it is hard set to 1'b1 external to this
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// peripheral.
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// peripheral.
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//
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//
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// initial q_rts = 1'b0;
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// initial q_cts_n = 1'b1;
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// initial qq_rts = 1'b0;
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// initial qq_cts_n = 1'b1;
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// initial ck_rts = 1'b0;
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// initial ck_cts = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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q_rts <= i_rts;
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q_cts_n <= i_cts_n;
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always @(posedge i_clk)
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always @(posedge i_clk)
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qq_rts <= q_rts;
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qq_cts_n <= q_cts_n;
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always @(posedge i_clk)
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always @(posedge i_clk)
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ck_rts <= (qq_rts)||(!hw_flow_control);
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ck_cts <= (!qq_cts_n)||(!hw_flow_control);
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initial o_uart_tx = 1'b1;
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initial o_uart_tx = 1'b1;
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initial r_busy = 1'b1;
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initial r_busy = 1'b1;
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initial state = `TXU_IDLE;
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initial state = `TXU_IDLE;
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initial lcl_data= 8'h0;
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initial lcl_data= 8'h0;
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Line 206... |
2'b01: state <= `TXU_BIT_ONE;
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2'b01: state <= `TXU_BIT_ONE;
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2'b10: state <= `TXU_BIT_TWO;
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2'b10: state <= `TXU_BIT_TWO;
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2'b11: state <= `TXU_BIT_THREE;
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2'b11: state <= `TXU_BIT_THREE;
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endcase
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endcase
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end else begin // Stay in idle
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end else begin // Stay in idle
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r_busy <= !ck_rts;
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r_busy <= !ck_cts;
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end
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end
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end else begin
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end else begin
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// One clock tick in each of these states ...
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// One clock tick in each of these states ...
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// baud_counter <= clocks_per_baud - 28'h01;
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// baud_counter <= clocks_per_baud - 28'h01;
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r_busy <= 1'b1;
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r_busy <= 1'b1;
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