| Line 91... |
Line 91... |
//
|
//
|
//
|
//
|
////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
//
|
//
|
//
|
//
|
|
`default_nettype none
|
|
//
|
`define TXU_BIT_ZERO 4'h0
|
`define TXU_BIT_ZERO 4'h0
|
`define TXU_BIT_ONE 4'h1
|
`define TXU_BIT_ONE 4'h1
|
`define TXU_BIT_TWO 4'h2
|
`define TXU_BIT_TWO 4'h2
|
`define TXU_BIT_THREE 4'h3
|
`define TXU_BIT_THREE 4'h3
|
`define TXU_BIT_FOUR 4'h4
|
`define TXU_BIT_FOUR 4'h4
|
| Line 112... |
Line 114... |
//
|
//
|
//
|
//
|
module txuart(i_clk, i_reset, i_setup, i_break, i_wr, i_data,
|
module txuart(i_clk, i_reset, i_setup, i_break, i_wr, i_data,
|
i_cts_n, o_uart_tx, o_busy);
|
i_cts_n, o_uart_tx, o_busy);
|
parameter [30:0] INITIAL_SETUP = 31'd868;
|
parameter [30:0] INITIAL_SETUP = 31'd868;
|
input i_clk, i_reset;
|
input wire i_clk, i_reset;
|
input [30:0] i_setup;
|
input wire [30:0] i_setup;
|
input i_break;
|
input wire i_break;
|
input i_wr;
|
input wire i_wr;
|
input [7:0] i_data;
|
input wire [7:0] i_data;
|
// Hardware flow control Ready-To-Send bit. Set this to one to use
|
// Hardware flow control Ready-To-Send bit. Set this to one to use
|
// the core without flow control. (A more appropriate name would be
|
// the core without flow control. (A more appropriate name would be
|
// the Ready-To-Receive bit ...)
|
// the Ready-To-Receive bit ...)
|
input i_cts_n;
|
input wire i_cts_n;
|
// And the UART input line itself
|
// And the UART input line itself
|
output reg o_uart_tx;
|
output reg o_uart_tx;
|
// A line to tell others when we are ready to accept data. If
|
// A line to tell others when we are ready to accept data. If
|
// (i_wr)&&(!o_busy) is ever true, then the core has accepted a byte
|
// (i_wr)&&(!o_busy) is ever true, then the core has accepted a byte
|
// for transmission.
|
// for transmission.
|
