| Line 114... |
Line 114... |
output reg o_uart_tx;
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output reg o_uart_tx;
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output wire o_busy;
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output wire o_busy;
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wire [27:0] clocks_per_baud, break_condition;
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wire [27:0] clocks_per_baud, break_condition;
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wire [1:0] data_bits;
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wire [1:0] data_bits;
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wire use_parity, parity_even, dblstop, fixd_parity;
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wire use_parity, parity_even, dblstop, fixd_parity,
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fixdp_value;
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reg [29:0] r_setup;
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reg [29:0] r_setup;
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assign clocks_per_baud = { 4'h0, r_setup[23:0] };
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assign clocks_per_baud = { 4'h0, r_setup[23:0] };
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assign break_condition = { r_setup[23:0], 4'h0 };
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assign break_condition = { r_setup[23:0], 4'h0 };
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assign data_bits = r_setup[29:28];
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assign data_bits = r_setup[29:28];
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assign dblstop = r_setup[27];
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assign dblstop = r_setup[27];
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assign use_parity = r_setup[26];
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assign use_parity = r_setup[26];
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assign fixd_parity = r_setup[25];
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assign fixd_parity = r_setup[25];
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assign parity_even = r_setup[24];
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assign parity_even = r_setup[24];
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assign fixdp_value = r_setup[24];
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reg [27:0] baud_counter;
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reg [27:0] baud_counter;
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reg [3:0] state;
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reg [3:0] state;
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reg [7:0] lcl_data;
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reg [7:0] lcl_data;
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reg calc_parity, r_busy, zero_baud_counter;
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reg calc_parity, r_busy, zero_baud_counter;
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initial r_setup = INITIAL_SETUP;
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initial o_uart_tx = 1'b1;
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initial o_uart_tx = 1'b1;
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initial r_busy = 1'b1;
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initial r_busy = 1'b1;
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initial state = `TXU_IDLE;
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initial state = `TXU_IDLE;
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initial lcl_data= 8'h0;
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initial lcl_data= 8'h0;
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initial calc_parity = 1'b0;
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initial calc_parity = 1'b0;
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// initial baud_counter = clocks_per_baud;//ILLEGAL--not constant
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// initial baud_counter = clocks_per_baud;//ILLEGAL--not constant
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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if (i_reset)
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if (i_reset)
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begin
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begin
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o_uart_tx <= 1'b1;
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r_busy <= 1'b1;
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r_busy <= 1'b1;
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state <= `TXU_IDLE;
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state <= `TXU_IDLE;
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lcl_data <= 8'h0;
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calc_parity <= 1'b0;
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end else if (i_break)
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end else if (i_break)
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begin
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begin
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o_uart_tx <= 1'b0;
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state <= `TXU_BREAK;
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state <= `TXU_BREAK;
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calc_parity <= 1'b0;
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r_busy <= 1'b1;
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r_busy <= 1'b1;
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end else if (~zero_baud_counter)
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end else if (!zero_baud_counter)
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begin // r_busy needs to be set coming into here
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begin // r_busy needs to be set coming into here
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r_busy <= 1'b1;
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r_busy <= 1'b1;
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end else if (state == `TXU_BREAK)
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end else if (state == `TXU_BREAK)
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begin
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begin
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state <= `TXU_IDLE;
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state <= `TXU_IDLE;
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r_busy <= 1'b1;
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r_busy <= 1'b1;
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o_uart_tx <= 1'b1;
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calc_parity <= 1'b0;
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end else if (state == `TXU_IDLE) // STATE_IDLE
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end else if (state == `TXU_IDLE) // STATE_IDLE
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begin
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begin
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// baud_counter <= 0;
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if ((i_wr)&&(!r_busy))
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r_setup <= i_setup;
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calc_parity <= 1'b0;
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if ((i_wr)&&(~r_busy))
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begin // Immediately start us off with a start bit
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begin // Immediately start us off with a start bit
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o_uart_tx <= 1'b0;
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r_busy <= 1'b1;
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r_busy <= 1'b1;
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case(data_bits)
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case(data_bits)
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2'b00: state <= `TXU_BIT_ZERO;
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2'b00: state <= `TXU_BIT_ZERO;
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2'b01: state <= `TXU_BIT_ONE;
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2'b01: state <= `TXU_BIT_ONE;
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2'b10: state <= `TXU_BIT_TWO;
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2'b10: state <= `TXU_BIT_TWO;
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2'b11: state <= `TXU_BIT_THREE;
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2'b11: state <= `TXU_BIT_THREE;
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endcase
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endcase
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lcl_data <= i_data;
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// baud_counter <= clocks_per_baud-28'h01;
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end else begin // Stay in idle
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end else begin // Stay in idle
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o_uart_tx <= 1'b1;
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r_busy <= 0;
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r_busy <= 0;
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// lcl_data is irrelevant
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// state <= state;
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end
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end
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end else begin
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end else begin
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// One clock tick in each of these states ...
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// One clock tick in each of these states ...
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// baud_counter <= clocks_per_baud - 28'h01;
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// baud_counter <= clocks_per_baud - 28'h01;
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r_busy <= 1'b1;
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r_busy <= 1'b1;
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if (state[3] == 0) // First 8 bits
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if (state[3] == 0) // First 8 bits
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begin
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begin
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o_uart_tx <= lcl_data[0];
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calc_parity <= calc_parity ^ lcl_data[0];
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if (state == `TXU_BIT_SEVEN)
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if (state == `TXU_BIT_SEVEN)
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state <= (use_parity)?`TXU_PARITY:`TXU_STOP;
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state <= (use_parity)?`TXU_PARITY:`TXU_STOP;
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else
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else
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state <= state + 1;
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state <= state + 1;
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lcl_data <= { 1'b0, lcl_data[7:1] };
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end else if (state == `TXU_PARITY)
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end else if (state == `TXU_PARITY)
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begin
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begin
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state <= `TXU_STOP;
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state <= `TXU_STOP;
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if (fixd_parity)
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o_uart_tx <= parity_even;
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else
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o_uart_tx <= calc_parity^((parity_even)? 1'b1:1'b0);
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end else if (state == `TXU_STOP)
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end else if (state == `TXU_STOP)
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begin // two stop bit(s)
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begin // two stop bit(s)
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o_uart_tx <= 1'b1;
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if (dblstop)
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if (dblstop)
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state <= `TXU_SECOND_STOP;
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state <= `TXU_SECOND_STOP;
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else
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else
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state <= `TXU_IDLE;
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state <= `TXU_IDLE;
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calc_parity <= 1'b0;
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end else // `TXU_SECOND_STOP and default:
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end else // `TXU_SECOND_STOP and default:
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begin
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begin
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state <= `TXU_IDLE; // Go back to idle
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state <= `TXU_IDLE; // Go back to idle
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o_uart_tx <= 1'b1;
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// Still r_busy, since we need to wait
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// Still r_busy, since we need to wait
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// for the baud clock to finish counting
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// for the baud clock to finish counting
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// out this last bit.
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// out this last bit.
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end
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end
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end
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end
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end
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end
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// o_busy
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//
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// This is a wire, designed to be true is we are ever busy above.
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// originally, this was going to be true if we were ever not in the
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// idle state. The logic has since become more complex, hence we have
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// a register dedicated to this and just copy out that registers value.
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assign o_busy = (r_busy);
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assign o_busy = (r_busy);
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// r_setup
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//
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// Our setup register. Accept changes between any pair of transmitted
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// words. The register itself has many fields to it. These are
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// broken out up top, and indicate what 1) our baud rate is, 2) our
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// number of stop bits, 3) what type of parity we are using, and 4)
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// the size of our data word.
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initial r_setup = INITIAL_SETUP;
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always @(posedge i_clk)
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if (state == `TXU_IDLE)
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r_setup <= i_setup;
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// lcl_data
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//
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// This is our working copy of the i_data register which we use
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// when transmitting. It is only of interest during transmit, and is
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// allowed to be whatever at any other time. Hence, if r_busy isn't
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// true, we can always set it. On the one clock where r_busy isn't
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// true and i_wr is, we set it and r_busy is true thereafter.
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// Then, on any zero_baud_counter (i.e. change between baud intervals)
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// we simple logically shift the register right to grab the next bit.
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always @(posedge i_clk)
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if (!r_busy)
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lcl_data <= i_data;
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else if (zero_baud_counter)
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lcl_data <= { 1'b0, lcl_data[7:1] };
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// o_uart_tx
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//
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// This is the final result/output desired of this core. It's all
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// centered about o_uart_tx. This is what finally needs to follow
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// the UART protocol.
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//
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// Ok, that said, our rules are:
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// 1'b0 on any break condition
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// 1'b0 on a start bit (IDLE, write, and not busy)
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// lcl_data[0] during any data transfer, but only at the baud
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// change
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// PARITY -- During the parity bit. This depends upon whether or
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// not the parity bit is fixed, then what it's fixed to,
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// or changing, and hence what it's calculated value is.
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// 1'b1 at all other times (stop bits, idle, etc)
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always @(posedge i_clk)
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if (i_reset)
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o_uart_tx <= 1'b1;
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else if ((i_break)||((i_wr)&&(!r_busy)))
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o_uart_tx <= 1'b0;
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else if (zero_baud_counter)
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casez(state)
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4'b0???: o_uart_tx <= lcl_data[0];
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`TXU_PARITY: o_uart_tx <= calc_parity;
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default: o_uart_tx <= 1'b1;
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endcase
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// calc_parity
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//
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// Calculate the parity to be placed into the parity bit. If the
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// parity is fixed, then the parity bit is given by the fixed parity
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// value (r_setup[24]). Otherwise the parity is given by the GF2
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// sum of all the data bits (plus one for even parity).
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always @(posedge i_clk)
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if (fixd_parity)
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calc_parity <= fixdp_value;
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else if (zero_baud_counter)
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begin
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if (state[3] == 0) // First 8 bits of msg
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calc_parity <= calc_parity ^ lcl_data[0];
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else
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calc_parity <= parity_even;
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end else if (!r_busy)
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calc_parity <= parity_even;
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// All of the above logic is driven by the baud counter. Bits must last
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// clocks_per_baud in length, and this baud counter is what we use to
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// make certain of that.
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//
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// The basic logic is this: at the beginning of a bit interval, start
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// the baud counter and set it to count clocks_per_baud. When it gets
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// to zero, restart it.
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//
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// However, comparing a 28'bit number to zero can be rather complex--
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// especially if we wish to do anything else on that same clock. For
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// that reason, we create "zero_baud_counter". zero_baud_counter is
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// nothing more than a flag that is true anytime baud_counter is zero.
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// It's true when the logic (above) needs to step to the next bit.
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// Simple enough?
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//
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// I wish we could stop there, but there are some other (ugly)
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// conditions to deal with that offer exceptions to this basic logic.
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//
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// 1. When the user has commanded a BREAK across the line, we need to
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// wait several baud intervals following the break before we start
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// transmitting, to give any receiver a chance to recognize that we are
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// out of the break condition, and to know that the next bit will be
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// a stop bit.
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//
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// 2. A reset is similar to a break condition--on both we wait several
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// baud intervals before allowing a start bit.
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//
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// 3. In the idle state, we stop our counter--so that upon a request
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// to transmit when idle we can start transmitting immediately, rather
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// than waiting for the end of the next (fictitious and arbitrary) baud
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// interval.
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//
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// When (i_wr)&&(!r_busy)&&(state == `TXU_IDLE) then we're not only in
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// the idle state, but we also just accepted a command to start writing
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// the next word. At this point, the baud counter needs to be reset
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// to the number of clocks per baud, and zero_baud_counter set to zero.
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//
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// The logic is a bit twisted here, in that it will only check for the
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// above condition when zero_baud_counter is false--so as to make
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// certain the STOP bit is complete.
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initial zero_baud_counter = 1'b0;
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initial zero_baud_counter = 1'b0;
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initial baud_counter = 28'h05;
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initial baud_counter = 28'h05;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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zero_baud_counter <= (baud_counter == 28'h01);
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zero_baud_counter <= (baud_counter == 28'h01);
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if ((i_reset)||(i_break))
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if ((i_reset)||(i_break))
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begin
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begin
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// Give ourselves 16 bauds before being ready
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// Give ourselves 16 bauds before being ready
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baud_counter <= break_condition;
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baud_counter <= break_condition;
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zero_baud_counter <= 1'b0;
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zero_baud_counter <= 1'b0;
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end else if (~zero_baud_counter)
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end else if (!zero_baud_counter)
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baud_counter <= baud_counter - 28'h01;
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baud_counter <= baud_counter - 28'h01;
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else if (state == `TXU_BREAK)
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else if (state == `TXU_BREAK)
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// Give us two stop bits before becoming available
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// Give us four idle baud intervals before becoming
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// available
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baud_counter <= clocks_per_baud<<2;
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baud_counter <= clocks_per_baud<<2;
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else if (state == `TXU_IDLE)
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else if (state == `TXU_IDLE)
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begin
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begin
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if((i_wr)&&(~r_busy))
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baud_counter <= 28'h0;
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baud_counter <= clocks_per_baud - 28'h01;
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else
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zero_baud_counter <= 1'b1;
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zero_baud_counter <= 1'b1;
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if ((i_wr)&&(!r_busy))
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begin
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baud_counter <= clocks_per_baud - 28'h01;
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zero_baud_counter <= 1'b0;
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end
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end else
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end else
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baud_counter <= clocks_per_baud - 28'h01;
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baud_counter <= clocks_per_baud - 28'h01;
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end
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end
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endmodule
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endmodule
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