| Line 19... |
Line 19... |
// There is a synchronous reset line, logic high.
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// There is a synchronous reset line, logic high.
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//
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//
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// Now for the setup register. The register is 32 bits, so that this
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// Now for the setup register. The register is 32 bits, so that this
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// UART may be set up over a 32-bit bus.
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// UART may be set up over a 32-bit bus.
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//
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//
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// i_setup[30] Set this to zero to use hardware flow control, and to
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// one to ignore hardware flow control. Only works if the hardware
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// flow control has been properly wired.
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//
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// If you don't want hardware flow control, fix the i_rts bit to
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// 1'b1, and let the synthesys tools optimize out the logic.
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//
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// i_setup[29:28] Indicates the number of data bits per word. This will
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// i_setup[29:28] Indicates the number of data bits per word. This will
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// either be 2'b00 for an 8-bit word, 2'b01 for a 7-bit word, 2'b10
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// either be 2'b00 for an 8-bit word, 2'b01 for a 7-bit word, 2'b10
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// for a six bit word, or 2'b11 for a five bit word.
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// for a six bit word, or 2'b11 for a five bit word.
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//
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//
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// i_setup[27] Indicates whether or not to use one or two stop bits.
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// i_setup[27] Indicates whether or not to use one or two stop bits.
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| Line 60... |
Line 67... |
// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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// Copyright (C) 2015-2017, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
|
// modify it under the terms of the GNU General Public License as published
|
// modify it under the terms of the GNU General Public License as published
|
// by the Free Software Foundation, either version 3 of the License, or (at
|
// by the Free Software Foundation, either version 3 of the License, or (at
|
// your option) any later version.
|
// your option) any later version.
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| Line 73... |
Line 80... |
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
|
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
// for more details.
|
// for more details.
|
//
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//
|
// You should have received a copy of the GNU General Public License along
|
// You should have received a copy of the GNU General Public License along
|
// with this program. (It's in the $(ROOT)/doc directory, run make with no
|
// with this program. (It's in the $(ROOT)/doc directory. Run make with no
|
// target there if the PDF file isn't present.) If not, see
|
// target there if the PDF file isn't present.) If not, see
|
// <http://www.gnu.org/licenses/> for a copy.
|
// <http://www.gnu.org/licenses/> for a copy.
|
//
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//
|
// License: GPL, v3, as defined and found on www.gnu.org,
|
// License: GPL, v3, as defined and found on www.gnu.org,
|
// http://www.gnu.org/licenses/gpl.html
|
// http://www.gnu.org/licenses/gpl.html
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| Line 102... |
Line 109... |
// `define TXU_START 4'hd // An unused state
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// `define TXU_START 4'hd // An unused state
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`define TXU_BREAK 4'he
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`define TXU_BREAK 4'he
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`define TXU_IDLE 4'hf
|
`define TXU_IDLE 4'hf
|
//
|
//
|
//
|
//
|
module txuart(i_clk, i_reset, i_setup, i_break, i_wr, i_data,o_uart_tx, o_busy);
|
module txuart(i_clk, i_reset, i_setup, i_break, i_wr, i_data,
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parameter INITIAL_SETUP = 30'd868;
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i_rts, o_uart_tx, o_busy);
|
|
parameter [30:0] INITIAL_SETUP = 31'd868;
|
input i_clk, i_reset;
|
input i_clk, i_reset;
|
input [29:0] i_setup;
|
input [30:0] i_setup;
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input i_break;
|
input i_break;
|
input i_wr;
|
input i_wr;
|
input [7:0] i_data;
|
input [7:0] i_data;
|
|
// Hardware flow control Ready-To-Send bit. Set this to one to use
|
|
// the core without flow control. (A more appropriate name would be
|
|
// the Ready-To-Receive bit ...)
|
|
input i_rts;
|
|
// And the UART input line itself
|
output reg o_uart_tx;
|
output reg o_uart_tx;
|
|
// A line to tell others when we are ready to accept data. If
|
|
// (i_wr)&&(!o_busy) is ever true, then the core has accepted a byte
|
|
// for transmission.
|
output wire o_busy;
|
output wire o_busy;
|
|
|
wire [27:0] clocks_per_baud, break_condition;
|
wire [27:0] clocks_per_baud, break_condition;
|
wire [1:0] data_bits;
|
wire [1:0] data_bits;
|
wire use_parity, parity_even, dblstop, fixd_parity,
|
wire use_parity, parity_even, dblstop, fixd_parity,
|
fixdp_value;
|
fixdp_value, hw_flow_control;
|
reg [29:0] r_setup;
|
reg [30:0] r_setup;
|
assign clocks_per_baud = { 4'h0, r_setup[23:0] };
|
assign clocks_per_baud = { 4'h0, r_setup[23:0] };
|
assign break_condition = { r_setup[23:0], 4'h0 };
|
assign break_condition = { r_setup[23:0], 4'h0 };
|
|
assign hw_flow_control = !r_setup[30];
|
assign data_bits = r_setup[29:28];
|
assign data_bits = r_setup[29:28];
|
assign dblstop = r_setup[27];
|
assign dblstop = r_setup[27];
|
assign use_parity = r_setup[26];
|
assign use_parity = r_setup[26];
|
assign fixd_parity = r_setup[25];
|
assign fixd_parity = r_setup[25];
|
assign parity_even = r_setup[24];
|
assign parity_even = r_setup[24];
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| Line 131... |
Line 148... |
reg [27:0] baud_counter;
|
reg [27:0] baud_counter;
|
reg [3:0] state;
|
reg [3:0] state;
|
reg [7:0] lcl_data;
|
reg [7:0] lcl_data;
|
reg calc_parity, r_busy, zero_baud_counter;
|
reg calc_parity, r_busy, zero_baud_counter;
|
|
|
|
|
|
// First step ... handle any hardware flow control, if so enabled.
|
|
//
|
|
// Clock in the flow control data, two clocks to avoid metastability
|
|
// Default to using hardware flow control (uart_setup[30]==0 to use it).
|
|
// Set this high order bit off if you do not wish to use it.
|
|
reg q_rts, qq_rts, ck_rts;
|
|
// While we might wish to give initial values to q_rts and ck_rts,
|
|
// 1) it's not required since the transmitter starts in a long wait
|
|
// state, and 2) doing so will prevent the synthesizer from optimizing
|
|
// this pin in the case it is hard set to 1'b1 external to this
|
|
// peripheral.
|
|
//
|
|
// initial q_rts = 1'b0;
|
|
// initial qq_rts = 1'b0;
|
|
// initial ck_rts = 1'b0;
|
|
always @(posedge i_clk)
|
|
q_rts <= i_rts;
|
|
always @(posedge i_clk)
|
|
qq_rts <= q_rts;
|
|
always @(posedge i_clk)
|
|
ck_rts <= (qq_rts)&&(hw_flow_control);
|
|
|
initial o_uart_tx = 1'b1;
|
initial o_uart_tx = 1'b1;
|
initial r_busy = 1'b1;
|
initial r_busy = 1'b1;
|
initial state = `TXU_IDLE;
|
initial state = `TXU_IDLE;
|
initial lcl_data= 8'h0;
|
initial lcl_data= 8'h0;
|
initial calc_parity = 1'b0;
|
initial calc_parity = 1'b0;
|
| Line 166... |
Line 206... |
2'b01: state <= `TXU_BIT_ONE;
|
2'b01: state <= `TXU_BIT_ONE;
|
2'b10: state <= `TXU_BIT_TWO;
|
2'b10: state <= `TXU_BIT_TWO;
|
2'b11: state <= `TXU_BIT_THREE;
|
2'b11: state <= `TXU_BIT_THREE;
|
endcase
|
endcase
|
end else begin // Stay in idle
|
end else begin // Stay in idle
|
r_busy <= 0;
|
r_busy <= !ck_rts;
|
end
|
end
|
end else begin
|
end else begin
|
// One clock tick in each of these states ...
|
// One clock tick in each of these states ...
|
// baud_counter <= clocks_per_baud - 28'h01;
|
// baud_counter <= clocks_per_baud - 28'h01;
|
r_busy <= 1'b1;
|
r_busy <= 1'b1;
|
| Line 213... |
Line 253... |
// Our setup register. Accept changes between any pair of transmitted
|
// Our setup register. Accept changes between any pair of transmitted
|
// words. The register itself has many fields to it. These are
|
// words. The register itself has many fields to it. These are
|
// broken out up top, and indicate what 1) our baud rate is, 2) our
|
// broken out up top, and indicate what 1) our baud rate is, 2) our
|
// number of stop bits, 3) what type of parity we are using, and 4)
|
// number of stop bits, 3) what type of parity we are using, and 4)
|
// the size of our data word.
|
// the size of our data word.
|
initial r_setup = INITIAL_SETUP;
|
initial r_setup = INITIAL_SETUP[30:0];
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (state == `TXU_IDLE)
|
if (state == `TXU_IDLE)
|
r_setup <= i_setup;
|
r_setup <= i_setup;
|
|
|
// lcl_data
|
// lcl_data
|
