| Line 47... |
Line 47... |
//
|
//
|
//
|
//
|
////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
//
|
//
|
//
|
//
|
`define TXU_BIT_ZERO 4'h0
|
`default_nettype none
|
`define TXU_BIT_ONE 4'h1
|
//
|
`define TXU_BIT_TWO 4'h2
|
`define TXUL_BIT_ZERO 4'h0
|
`define TXU_BIT_THREE 4'h3
|
`define TXUL_BIT_ONE 4'h1
|
`define TXU_BIT_FOUR 4'h4
|
`define TXUL_BIT_TWO 4'h2
|
`define TXU_BIT_FIVE 4'h5
|
`define TXUL_BIT_THREE 4'h3
|
`define TXU_BIT_SIX 4'h6
|
`define TXUL_BIT_FOUR 4'h4
|
`define TXU_BIT_SEVEN 4'h7
|
`define TXUL_BIT_FIVE 4'h5
|
`define TXU_STOP 4'h8
|
`define TXUL_BIT_SIX 4'h6
|
`define TXU_IDLE 4'hf
|
`define TXUL_BIT_SEVEN 4'h7
|
|
`define TXUL_STOP 4'h8
|
|
`define TXUL_IDLE 4'hf
|
//
|
//
|
//
|
//
|
module txuartlite(i_clk, i_wr, i_data, o_uart_tx, o_busy);
|
module txuartlite(i_clk, i_wr, i_data, o_uart_tx, o_busy);
|
parameter [23:0] CLOCKS_PER_BAUD = 24'd868;
|
parameter [23:0] CLOCKS_PER_BAUD = 24'd868;
|
input i_clk;
|
input wire i_clk;
|
input i_wr;
|
input wire i_wr;
|
input [7:0] i_data;
|
input wire [7:0] i_data;
|
// And the UART input line itself
|
// And the UART input line itself
|
output reg o_uart_tx;
|
output reg o_uart_tx;
|
// A line to tell others when we are ready to accept data. If
|
// A line to tell others when we are ready to accept data. If
|
// (i_wr)&&(!o_busy) is ever true, then the core has accepted a byte
|
// (i_wr)&&(!o_busy) is ever true, then the core has accepted a byte
|
// for transmission.
|
// for transmission.
|
| Line 77... |
Line 79... |
reg [3:0] state;
|
reg [3:0] state;
|
reg [7:0] lcl_data;
|
reg [7:0] lcl_data;
|
reg r_busy, zero_baud_counter;
|
reg r_busy, zero_baud_counter;
|
|
|
initial r_busy = 1'b1;
|
initial r_busy = 1'b1;
|
initial state = `TXU_IDLE;
|
initial state = `TXUL_IDLE;
|
initial lcl_data= 8'h0;
|
initial lcl_data= 8'h0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
begin
|
begin
|
if (!zero_baud_counter)
|
if (!zero_baud_counter)
|
// r_busy needs to be set coming into here
|
// r_busy needs to be set coming into here
|
r_busy <= 1'b1;
|
r_busy <= 1'b1;
|
else if (state == `TXU_IDLE) // STATE_IDLE
|
else if (state == `TXUL_IDLE) // STATE_IDLE
|
begin
|
begin
|
r_busy <= 1'b0;
|
r_busy <= 1'b0;
|
if ((i_wr)&&(!r_busy))
|
if ((i_wr)&&(!r_busy))
|
begin // Immediately start us off with a start bit
|
begin // Immediately start us off with a start bit
|
r_busy <= 1'b1;
|
r_busy <= 1'b1;
|
state <= `TXU_BIT_ZERO;
|
state <= `TXUL_BIT_ZERO;
|
end
|
end
|
end else begin
|
end else begin
|
// One clock tick in each of these states ...
|
// One clock tick in each of these states ...
|
r_busy <= 1'b1;
|
r_busy <= 1'b1;
|
if (state <=`TXU_STOP) // start bit, 8-d bits, stop-b
|
if (state <=`TXUL_STOP) // start bit, 8-d bits, stop-b
|
state <= state + 1;
|
state <= state + 1;
|
else
|
else
|
state <= `TXU_IDLE;
|
state <= `TXUL_IDLE;
|
end
|
end
|
end
|
end
|
|
|
// o_busy
|
// o_busy
|
//
|
//
|
| Line 173... |
Line 175... |
// 3. In the idle state, we stop our counter--so that upon a request
|
// 3. In the idle state, we stop our counter--so that upon a request
|
// to transmit when idle we can start transmitting immediately, rather
|
// to transmit when idle we can start transmitting immediately, rather
|
// than waiting for the end of the next (fictitious and arbitrary) baud
|
// than waiting for the end of the next (fictitious and arbitrary) baud
|
// interval.
|
// interval.
|
//
|
//
|
// When (i_wr)&&(!r_busy)&&(state == `TXU_IDLE) then we're not only in
|
// When (i_wr)&&(!r_busy)&&(state == `TXUL_IDLE) then we're not only in
|
// the idle state, but we also just accepted a command to start writing
|
// the idle state, but we also just accepted a command to start writing
|
// the next word. At this point, the baud counter needs to be reset
|
// the next word. At this point, the baud counter needs to be reset
|
// to the number of CLOCKS_PER_BAUD, and zero_baud_counter set to zero.
|
// to the number of CLOCKS_PER_BAUD, and zero_baud_counter set to zero.
|
//
|
//
|
// The logic is a bit twisted here, in that it will only check for the
|
// The logic is a bit twisted here, in that it will only check for the
|
| Line 186... |
Line 188... |
initial zero_baud_counter = 1'b0;
|
initial zero_baud_counter = 1'b0;
|
initial baud_counter = 24'h05;
|
initial baud_counter = 24'h05;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
begin
|
begin
|
zero_baud_counter <= (baud_counter == 24'h01);
|
zero_baud_counter <= (baud_counter == 24'h01);
|
if (state == `TXU_IDLE)
|
if (state == `TXUL_IDLE)
|
begin
|
begin
|
baud_counter <= 24'h0;
|
baud_counter <= 24'h0;
|
zero_baud_counter <= 1'b1;
|
zero_baud_counter <= 1'b1;
|
if ((i_wr)&&(!r_busy))
|
if ((i_wr)&&(!r_busy))
|
begin
|
begin
|
