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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015-2017, Gisselquist Technology, LLC
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// Copyright (C) 2015-2019, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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//
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//
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module txuartlite(i_clk, i_wr, i_data, o_uart_tx, o_busy);
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module txuartlite(i_clk, i_wr, i_data, o_uart_tx, o_busy);
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parameter [4:0] TIMING_BITS = 5'd24;
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parameter [4:0] TIMING_BITS = 5'd24;
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localparam TB = TIMING_BITS;
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localparam TB = TIMING_BITS;
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parameter [(TB-1):0] CLOCKS_PER_BAUD = 8; // 24'd868;
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parameter [(TB-1):0] CLOCKS_PER_BAUD = 8; // 24'd868;
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parameter [0:0] F_OPT_CLK2FFLOGIC = 1'b0;
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input wire i_clk;
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input wire i_clk;
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input wire i_wr;
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input wire i_wr;
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input wire [7:0] i_data;
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input wire [7:0] i_data;
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// And the UART input line itself
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// And the UART input line itself
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output reg o_uart_tx;
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output reg o_uart_tx;
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// certain the STOP bit is complete.
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// certain the STOP bit is complete.
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initial zero_baud_counter = 1'b1;
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initial zero_baud_counter = 1'b1;
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initial baud_counter = 0;
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initial baud_counter = 0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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zero_baud_counter <= (baud_counter == 24'h01);
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zero_baud_counter <= (baud_counter == 1);
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if (state == `TXUL_IDLE)
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if (state == `TXUL_IDLE)
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begin
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begin
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baud_counter <= 24'h0;
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baud_counter <= 0;
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zero_baud_counter <= 1'b1;
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zero_baud_counter <= 1'b1;
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if ((i_wr)&&(!r_busy))
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if ((i_wr)&&(!r_busy))
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begin
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begin
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baud_counter <= CLOCKS_PER_BAUD - 24'h01;
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baud_counter <= CLOCKS_PER_BAUD - 1'b1;
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zero_baud_counter <= 1'b0;
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zero_baud_counter <= 1'b0;
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end
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end
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end else if ((zero_baud_counter)&&(state == 4'h9))
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end else if ((zero_baud_counter)&&(state == 4'h9))
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begin
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begin
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baud_counter <= 0;
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baud_counter <= 0;
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zero_baud_counter <= 1'b1;
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zero_baud_counter <= 1'b1;
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end else if (!zero_baud_counter)
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end else if (!zero_baud_counter)
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baud_counter <= baud_counter - 24'h01;
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baud_counter <= baud_counter - 1'b1;
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else
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else
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baud_counter <= CLOCKS_PER_BAUD - 24'h01;
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baud_counter <= CLOCKS_PER_BAUD - 1'b1;
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end
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end
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//
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//
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//
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//
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// FORMAL METHODS
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// FORMAL METHODS
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// Setup
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// Setup
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reg f_past_valid, f_last_clk;
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reg f_past_valid, f_last_clk;
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generate if (F_OPT_CLK2FFLOGIC)
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begin
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always @($global_clock)
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begin
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restrict(i_clk == !f_last_clk);
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f_last_clk <= i_clk;
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if (!$rose(i_clk))
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begin
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`ASSUME($stable(i_wr));
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`ASSUME($stable(i_data));
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end
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end
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end endgenerate
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initial f_past_valid = 1'b0;
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initial f_past_valid = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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f_past_valid <= 1'b1;
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f_past_valid <= 1'b1;
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initial `ASSUME(!i_wr);
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initial `ASSUME(!i_wr);
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