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Line 36... |
//
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//
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//
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//
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module ufifo(i_clk, i_rst, i_wr, i_data, o_empty_n, i_rd, o_data, o_status, o_err);
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module ufifo(i_clk, i_rst, i_wr, i_data, o_empty_n, i_rd, o_data, o_status, o_err);
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parameter BW=8; // Byte/data width
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parameter BW=8; // Byte/data width
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parameter [3:0] LGFLEN=4;
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parameter [3:0] LGFLEN=4;
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parameter [0:0] RXFIFO=0;
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parameter RXFIFO=1'b0;
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input i_clk, i_rst;
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input i_clk, i_rst;
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input i_wr;
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input i_wr;
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input [(BW-1):0] i_data;
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input [(BW-1):0] i_data;
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output wire o_empty_n; // True if something is in FIFO
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output wire o_empty_n; // True if something is in FIFO
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input i_rd;
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input i_rd;
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// the FIFO count that matters is the number of empty positions that
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// the FIFO count that matters is the number of empty positions that
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// can still be filled before the FIFO is full.
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// can still be filled before the FIFO is full.
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//
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//
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// Adjust for these differences here.
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// Adjust for these differences here.
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reg [(LGFLEN-1):0] r_fill;
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reg [(LGFLEN-1):0] r_fill;
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generate if (RXFIFO!=0) begin
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always @(posedge i_clk)
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if (RXFIFO!=0) begin
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// Calculate the number of elements in our FIFO
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// Calculate the number of elements in our FIFO
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//
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//
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// Although used for receive, this is actually the more generic
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// Although used for receive, this is actually the more
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// answer--should you wish to use the FIFO in another context.
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// generic answer--should you wish to use the FIFO in
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always @(posedge i_clk)
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// another context.
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if (i_rst)
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if (i_rst)
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r_fill <= 0;
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r_fill <= 0;
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else case({i_wr, i_rd})
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else case({i_wr, i_rd})
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2'b01: r_fill <= r_first - r_next;
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2'b01: r_fill <= r_first - r_next;
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2'b10: r_fill <= r_first - r_last + 1'b1;
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2'b10: r_fill <= r_first - r_last + 1'b1;
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default: r_fill <= r_first - r_last;
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default: r_fill <= r_first - r_last;
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endcase
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endcase
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end else begin
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end else begin
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// Calculate the number of elements that are empty and can be
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// Calculate the number of elements that are empty and
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// filled within our FIFO
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// can be filled within our FIFO
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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r_fill <= { (LGFLEN){1'b1} };
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r_fill <= { (LGFLEN){1'b1} };
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else case({i_wr, i_rd})
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else case({i_wr, i_rd})
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2'b01: r_fill <= r_last - r_first;
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2'b01: r_fill <= r_last - r_first;
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2'b10: r_fill <= r_last - w_first_plus_two;
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2'b10: r_fill <= r_last - w_first_plus_two;
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default: r_fill <= r_last - w_first_plus_one;
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default: r_fill <= r_last - w_first_plus_one;
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endcase
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endcase
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end endgenerate
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end
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// We don't report underflow errors. These
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// We don't report underflow errors. These
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assign o_err = (r_ovfl); // || (r_unfl);
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assign o_err = (r_ovfl); // || (r_unfl);
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wire [3:0] lglen;
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wire [3:0] lglen;
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assign lglen = LGFLEN;
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assign lglen = LGFLEN;
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wire [9:0] w_fill;
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wire [9:0] w_fill;
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assign w_fill[(LGFLEN-1):0] = r_fill;
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assign w_fill[(LGFLEN-1):0] = r_fill;
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generate if (LGFLEN != 10)
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generate if (LGFLEN < 10)
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assign w_fill[9:(LGFLEN-1)] = 0;
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assign w_fill[9:(LGFLEN)] = 0;
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endgenerate
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endgenerate
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wire w_half_full;
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wire w_half_full;
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assign w_half_full = r_fill[(LGFLEN-1)];
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assign w_half_full = r_fill[(LGFLEN-1)];
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