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Line 33... |
//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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`default_nettype none
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//
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module ufifo(i_clk, i_rst, i_wr, i_data, o_empty_n, i_rd, o_data, o_status, o_err);
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module ufifo(i_clk, i_rst, i_wr, i_data, o_empty_n, i_rd, o_data, o_status, o_err);
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parameter BW=8; // Byte/data width
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parameter BW=8; // Byte/data width
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parameter [3:0] LGFLEN=4;
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parameter [3:0] LGFLEN=4;
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parameter RXFIFO=1'b0;
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parameter RXFIFO=1'b0;
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input i_clk, i_rst;
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input wire i_clk, i_rst;
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input i_wr;
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input wire i_wr;
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input [(BW-1):0] i_data;
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input wire [(BW-1):0] i_data;
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output wire o_empty_n; // True if something is in FIFO
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output wire o_empty_n; // True if something is in FIFO
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input i_rd;
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input wire i_rd;
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output wire [(BW-1):0] o_data;
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output wire [(BW-1):0] o_data;
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output wire [15:0] o_status;
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output wire [15:0] o_status;
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output wire o_err;
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output wire o_err;
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localparam FLEN=(1<<LGFLEN);
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localparam FLEN=(1<<LGFLEN);
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if (i_rst)
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if (i_rst)
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will_overflow <= 1'b0;
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will_overflow <= 1'b0;
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else if (i_rd)
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else if (i_rd)
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will_overflow <= (will_overflow)&&(i_wr);
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will_overflow <= (will_overflow)&&(i_wr);
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else if (i_wr)
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else if (i_wr)
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will_overflow <= (w_first_plus_two == r_last);
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will_overflow <= (will_overflow)||(w_first_plus_two == r_last);
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else if (w_first_plus_one == r_last)
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else if (w_first_plus_one == r_last)
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will_overflow <= 1'b1;
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will_overflow <= 1'b1;
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// Write
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// Write
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reg r_ovfl;
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reg r_ovfl;
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if (i_rst)
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if (i_rst)
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will_underflow <= 1'b1;
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will_underflow <= 1'b1;
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else if (i_wr)
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else if (i_wr)
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will_underflow <= (will_underflow)&&(i_rd);
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will_underflow <= (will_underflow)&&(i_rd);
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else if (i_rd)
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else if (i_rd)
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will_underflow <= (w_last_plus_one == r_first);
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will_underflow <= (will_underflow)||(w_last_plus_one == r_first);
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else
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else
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will_underflow <= (r_last == r_first);
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will_underflow <= (r_last == r_first);
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//
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//
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// Don't report FIFO underflow errors. These'll be caught elsewhere
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// Don't report FIFO underflow errors. These'll be caught elsewhere
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// o_data <= fifo[r_last+1];
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// o_data <= fifo[r_last+1];
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end
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end
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// else r_unfl <= 1'b1;
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// else r_unfl <= 1'b1;
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end
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end
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reg [7:0] fifo_here, fifo_next, r_data;
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reg [(BW-1):0] fifo_here, fifo_next, r_data;
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always @(posedge i_clk)
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always @(posedge i_clk)
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fifo_here <= fifo[r_last];
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fifo_here <= fifo[r_last];
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always @(posedge i_clk)
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always @(posedge i_clk)
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fifo_next <= fifo[r_next];
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fifo_next <= fifo[r_next];
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always @(posedge i_clk)
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always @(posedge i_clk)
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reg r_empty_n;
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reg r_empty_n;
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initial r_empty_n = 1'b0;
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initial r_empty_n = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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r_empty_n <= 1'b0;
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r_empty_n <= 1'b0;
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else case({i_wr, i_rd})
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else casez({i_wr, i_rd, will_underflow})
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2'b00: r_empty_n <= (r_first != r_last);
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3'b00?: r_empty_n <= (r_first != r_last);
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2'b11: r_empty_n <= (r_first != r_last);
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3'b11?: r_empty_n <= (r_first != r_last);
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2'b10: r_empty_n <= 1'b1;
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3'b10?: r_empty_n <= 1'b1;
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2'b01: r_empty_n <= (r_first != w_last_plus_one);
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3'b010: r_empty_n <= (r_first != w_last_plus_one);
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// 3'b001: r_empty_n <= 1'b0;
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default: begin end
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endcase
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endcase
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wire w_full_n;
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wire w_full_n;
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assign w_full_n = will_overflow;
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assign w_full_n = will_overflow;
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// the FIFO count that matters is the number of empty positions that
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// the FIFO count that matters is the number of empty positions that
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// can still be filled before the FIFO is full.
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// can still be filled before the FIFO is full.
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//
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//
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// Adjust for these differences here.
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// Adjust for these differences here.
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reg [(LGFLEN-1):0] r_fill;
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reg [(LGFLEN-1):0] r_fill;
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initial r_fill = 0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (RXFIFO!=0) begin
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if (RXFIFO!=0) begin
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// Calculate the number of elements in our FIFO
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// Calculate the number of elements in our FIFO
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//
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//
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// Although used for receive, this is actually the more
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// Although used for receive, this is actually the more
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// generic answer--should you wish to use the FIFO in
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// generic answer--should you wish to use the FIFO in
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// another context.
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// another context.
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if (i_rst)
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if (i_rst)
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r_fill <= 0;
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r_fill <= 0;
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else case({i_wr, i_rd})
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else case({(i_wr)&&(!will_overflow), (i_rd)&&(!will_underflow)})
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2'b01: r_fill <= r_first - r_next;
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2'b01: r_fill <= r_first - r_next;
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2'b10: r_fill <= r_first - r_last + 1'b1;
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2'b10: r_fill <= r_first - r_last + 1'b1;
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default: r_fill <= r_first - r_last;
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default: r_fill <= r_first - r_last;
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endcase
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endcase
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end else begin
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end else begin
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// Calculate the number of elements that are empty and
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// Calculate the number of elements that are empty and
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// can be filled within our FIFO
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// can be filled within our FIFO. Hence, this is really
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// not the fill, but (SIZE-1)-fill.
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if (i_rst)
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if (i_rst)
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r_fill <= { (LGFLEN){1'b1} };
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r_fill <= { (LGFLEN){1'b1} };
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else case({i_wr, i_rd})
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else case({i_wr, i_rd})
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2'b01: r_fill <= r_last - r_first;
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2'b01: r_fill <= r_last - r_first;
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2'b10: r_fill <= r_last - w_first_plus_two;
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2'b10: r_fill <= r_last - w_first_plus_two;
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