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//
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//
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// Filename: ufifo.v
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// Filename: ufifo.v
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//
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//
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// Project: wbuart32, a full featured UART with simulator
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// Project: wbuart32, a full featured UART with simulator
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//
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//
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// Purpose:
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// Purpose: A synchronous data FIFO, designed for supporting the Wishbone
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// UART. Particular features include the ability to read and
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// write on the same clock, while maintaining the correct output FIFO
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// parameters. Two versions of the FIFO exist within this file, separated
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// by the RXFIFO parameter's value. One, where RXFIFO = 1, produces status
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// values appropriate for reading and checking a read FIFO from logic,
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// whereas the RXFIFO = 0 applies to writing to the FIFO from bus logic
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// and reading it automatically any time the transmit UART is idle.
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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Line 116... |
initial will_underflow = 1'b1;
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initial will_underflow = 1'b1;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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will_underflow <= 1'b1;
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will_underflow <= 1'b1;
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else if (i_wr)
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else if (i_wr)
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will_underflow <= (will_underflow)&&(i_rd);
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will_underflow <= 1'b0;
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else if (i_rd)
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else if (i_rd)
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will_underflow <= (will_underflow)||(w_last_plus_one == r_first);
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will_underflow <= (will_underflow)||(w_last_plus_one == r_first);
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else
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else
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will_underflow <= (r_last == r_first);
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will_underflow <= (r_last == r_first);
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// We'll still report FIFO overflow, however.
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// We'll still report FIFO overflow, however.
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//
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//
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// reg r_unfl;
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// reg r_unfl;
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// initial r_unfl = 1'b0;
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// initial r_unfl = 1'b0;
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initial r_last = 0;
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initial r_last = 0;
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initial r_next = { {(LGFLEN-1){1'b0}}, 1'b1 };
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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begin
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begin
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r_last <= 0;
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r_last <= 0;
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r_next <= { {(LGFLEN-1){1'b0}}, 1'b1 };
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r_next <= { {(LGFLEN-1){1'b0}}, 1'b1 };
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// r_unfl <= 1'b0;
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// r_unfl <= 1'b0;
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end else if (i_rd)
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end else if (i_rd)
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begin
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begin
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if ((i_wr)||(!will_underflow)) // (r_first != r_last)
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if (!will_underflow) // (r_first != r_last)
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begin
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begin
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r_last <= r_next;
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r_last <= r_next;
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r_next <= r_last +{{(LGFLEN-2){1'b0}},2'b10};
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r_next <= r_last +{{(LGFLEN-2){1'b0}},2'b10};
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// Last chases first
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// Last chases first
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// Need to be prepared for a possible two
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// Need to be prepared for a possible two
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Line 182... |
always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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r_empty_n <= 1'b0;
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r_empty_n <= 1'b0;
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else casez({i_wr, i_rd, will_underflow})
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else casez({i_wr, i_rd, will_underflow})
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3'b00?: r_empty_n <= (r_first != r_last);
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3'b00?: r_empty_n <= (r_first != r_last);
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3'b11?: r_empty_n <= (r_first != r_last);
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3'b10?: r_empty_n <= 1'b1;
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3'b010: r_empty_n <= (r_first != w_last_plus_one);
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3'b010: r_empty_n <= (r_first != w_last_plus_one);
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// 3'b001: r_empty_n <= 1'b0;
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3'b10?: r_empty_n <= 1'b1;
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3'b110: r_empty_n <= (r_first != r_last);
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3'b111: r_empty_n <= 1'b1;
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default: begin end
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default: begin end
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endcase
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endcase
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wire w_full_n;
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wire w_full_n;
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assign w_full_n = will_overflow;
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assign w_full_n = will_overflow;
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// the FIFO count that matters is the number of empty positions that
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// the FIFO count that matters is the number of empty positions that
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// can still be filled before the FIFO is full.
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// can still be filled before the FIFO is full.
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//
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//
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// Adjust for these differences here.
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// Adjust for these differences here.
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reg [(LGFLEN-1):0] r_fill;
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reg [(LGFLEN-1):0] r_fill;
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generate
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if (RXFIFO != 0)
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initial r_fill = 0;
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initial r_fill = 0;
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else
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initial r_fill = -1;
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endgenerate
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (RXFIFO!=0) begin
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if (RXFIFO!=0) begin
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// Calculate the number of elements in our FIFO
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// Calculate the number of elements in our FIFO
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//
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//
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// Although used for receive, this is actually the more
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// Although used for receive, this is actually the more
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// generic answer--should you wish to use the FIFO in
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// generic answer--should you wish to use the FIFO in
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// another context.
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// another context.
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if (i_rst)
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if (i_rst)
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r_fill <= 0;
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r_fill <= 0;
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else case({(i_wr)&&(!will_overflow), (i_rd)&&(!will_underflow)})
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else casez({(i_wr), (!will_overflow), (i_rd)&&(!will_underflow)})
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2'b01: r_fill <= r_first - r_next;
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3'b0?1: r_fill <= r_first - r_next;
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2'b10: r_fill <= r_first - r_last + 1'b1;
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3'b110: r_fill <= r_first - r_last + 1'b1;
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3'b1?1: r_fill <= r_first - r_last;
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default: r_fill <= r_first - r_last;
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default: r_fill <= r_first - r_last;
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endcase
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endcase
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end else begin
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end else begin
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// Calculate the number of elements that are empty and
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// Calculate the number of elements that are empty and
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// can be filled within our FIFO. Hence, this is really
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// can be filled within our FIFO. Hence, this is really
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// not the fill, but (SIZE-1)-fill.
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// not the fill, but (SIZE-1)-fill.
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if (i_rst)
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if (i_rst)
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r_fill <= { (LGFLEN){1'b1} };
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r_fill <= { (LGFLEN){1'b1} };
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else case({i_wr, i_rd})
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else casez({i_wr, (!will_overflow), (i_rd)&&(!will_underflow)})
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2'b01: r_fill <= r_last - r_first;
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3'b0?1: r_fill <= r_fill + 1'b1;
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2'b10: r_fill <= r_last - w_first_plus_two;
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3'b110: r_fill <= r_fill - 1'b1;
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default: r_fill <= r_last - w_first_plus_one;
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default: r_fill <= r_fill;
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endcase
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endcase
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end
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end
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// We don't report underflow errors. These
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// We don't report underflow errors. These
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assign o_err = (r_ovfl); // || (r_unfl);
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assign o_err = (r_ovfl); // || (r_unfl);
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wire [3:0] lglen;
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wire [3:0] lglen;
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assign lglen = LGFLEN;
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assign lglen = LGFLEN;
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wire w_half_full;
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wire [9:0] w_fill;
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wire [9:0] w_fill;
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assign w_fill[(LGFLEN-1):0] = r_fill;
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assign w_fill[(LGFLEN-1):0] = r_fill;
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generate if (LGFLEN < 10)
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generate if (LGFLEN < 10)
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assign w_fill[9:(LGFLEN)] = 0;
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assign w_fill[9:(LGFLEN)] = 0;
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endgenerate
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endgenerate
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wire w_half_full;
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assign w_half_full = r_fill[(LGFLEN-1)];
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assign w_half_full = r_fill[(LGFLEN-1)];
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assign o_status = {
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assign o_status = {
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// Our status includes a 4'bit nibble telling anyone reading
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// Our status includes a 4'bit nibble telling anyone reading
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// this the size of our FIFO. The size is then given by
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// this the size of our FIFO. The size is then given by
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| Line 256... |
Line 271... |
(RXFIFO!=0)?r_empty_n:w_full_n
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(RXFIFO!=0)?r_empty_n:w_full_n
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};
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};
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assign o_empty_n = r_empty_n;
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assign o_empty_n = r_empty_n;
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//
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//
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//
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// FORMAL METHODS
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//
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//
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//
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`ifdef FORMAL
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`ifdef UFIFO
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`define ASSUME assume
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`else
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`define ASSUME assert
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`endif
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//
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// Assumptions about our input(s)
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//
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//
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reg f_past_valid, f_last_clk;
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initial restrict(i_rst);
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always @($global_clock)
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begin
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restrict(i_clk == !f_last_clk);
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f_last_clk <= i_clk;
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if (!$rose(i_clk))
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begin
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`ASSUME($stable(i_rst));
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`ASSUME($stable(i_wr));
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`ASSUME($stable(i_data));
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`ASSUME($stable(i_rd));
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end
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end
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//
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// Underflows are a very real possibility, should the user wish to
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// read from this FIFO while it is empty. Our parent module will need
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// to deal with this.
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//
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// always @(posedge i_clk)
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// `ASSUME((!will_underflow)||(!i_rd)||(i_rst));
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//
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// Assertions about our outputs
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//
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//
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initial f_past_valid = 1'b0;
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always @(posedge i_clk)
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f_past_valid <= 1'b1;
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wire [(LGFLEN-1):0] f_fill, f_next, f_empty;
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assign f_fill = r_first - r_last;
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assign f_empty = {(LGFLEN){1'b1}} -f_fill;
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assign f_next = r_last + 1'b1;
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always @(posedge i_clk)
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begin
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if (RXFIFO)
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assert(f_fill == r_fill);
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else
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assert(f_empty== r_fill);
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if (f_fill == 0)
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begin
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assert(will_underflow);
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assert(!o_empty_n);
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end else begin
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assert(!will_underflow);
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assert(o_empty_n);
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end
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if (f_fill == {(LGFLEN){1'b1}})
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assert(will_overflow);
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else
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assert(!will_overflow);
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assert(r_next == f_next);
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end
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always @(posedge i_clk)
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if (f_past_valid)
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begin
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if ($past(i_rst))
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assert(!o_err);
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else begin
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// No underflow detection in this core
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//
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// if (($past(i_rd))&&($past(r_fill == 0)))
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// assert(o_err);
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//
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// We do, though, have overflow detection
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if (($past(i_wr))&&(!$past(i_rd))
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&&($past(will_overflow)))
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assert(o_err);
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end
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end
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`endif
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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