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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015-2017, Gisselquist Technology, LLC
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// Copyright (C) 2015-2018, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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//
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//
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module ufifo(i_clk, i_rst, i_wr, i_data, o_empty_n, i_rd, o_data, o_status, o_err);
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module ufifo(i_clk, i_rst, i_wr, i_data, o_empty_n, i_rd, o_data, o_status, o_err);
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parameter BW=8; // Byte/data width
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parameter BW=8; // Byte/data width
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parameter [3:0] LGFLEN=4;
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parameter [3:0] LGFLEN=4;
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parameter RXFIFO=1'b0;
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parameter RXFIFO=1'b0;
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parameter [0:0] F_OPT_CLK2FFLOGIC = 1'b0;
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input wire i_clk, i_rst;
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input wire i_clk, i_rst;
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input wire i_wr;
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input wire i_wr;
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input wire [(BW-1):0] i_data;
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input wire [(BW-1):0] i_data;
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output wire o_empty_n; // True if something is in FIFO
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output wire o_empty_n; // True if something is in FIFO
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input wire i_rd;
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input wire i_rd;
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//
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//
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reg f_past_valid, f_last_clk;
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reg f_past_valid, f_last_clk;
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initial restrict(i_rst);
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initial restrict(i_rst);
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generate if (F_OPT_CLK2FFLOGIC)
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begin
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always @($global_clock)
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always @($global_clock)
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begin
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begin
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restrict(i_clk == !f_last_clk);
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restrict(i_clk == !f_last_clk);
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f_last_clk <= i_clk;
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f_last_clk <= i_clk;
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if (!$rose(i_clk))
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if (!$rose(i_clk))
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`ASSUME($stable(i_wr));
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`ASSUME($stable(i_wr));
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`ASSUME($stable(i_data));
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`ASSUME($stable(i_data));
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`ASSUME($stable(i_rd));
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`ASSUME($stable(i_rd));
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end
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end
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end
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end
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end endgenerate
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//
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//
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// Underflows are a very real possibility, should the user wish to
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// Underflows are a very real possibility, should the user wish to
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// read from this FIFO while it is empty. Our parent module will need
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// read from this FIFO while it is empty. Our parent module will need
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// to deal with this.
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// to deal with this.
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