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https://opencores.org/ocsvn/wbuart32/wbuart32/trunk
[/] [wbuart32/] [trunk/] [rtl/] [ufifo.v] - Diff between revs 23 and 24
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| Rev 23 |
Rev 24 |
| Line 267... |
Line 267... |
// FIFO) or written to (not a receive FIFO).
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// FIFO) or written to (not a receive FIFO).
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// receive FIFO), or be written to (if it isn't).
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// receive FIFO), or be written to (if it isn't).
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(RXFIFO!=0)?w_half_full:w_half_full,
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(RXFIFO!=0)?w_half_full:w_half_full,
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// A '1' here means the FIFO can be read from (if it is a
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// A '1' here means the FIFO can be read from (if it is a
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// receive FIFO), or be written to (if it isn't).
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// receive FIFO), or be written to (if it isn't).
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(RXFIFO!=0)?r_empty_n:w_full_n
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(RXFIFO!=0)?r_empty_n:!w_full_n
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};
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};
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assign o_empty_n = r_empty_n;
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assign o_empty_n = r_empty_n;
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//
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//
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| Line 382... |
Line 382... |
end
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end
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (!RXFIFO) // Transmit FIFO interrupt flags
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if (!RXFIFO) // Transmit FIFO interrupt flags
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begin
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begin
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assert(o_status[0] != (!w_full_n));
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assert(o_status[0] == (!w_full_n));
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assert(o_status[1] == (!f_fill[LGFLEN-1]));
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assert(o_status[1] == (!f_fill[LGFLEN-1]));
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end
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end
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`endif
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`endif
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endmodule
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endmodule
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