| Line 16... |
Line 16... |
// Creator: Dan Gisselquist, Ph.D.
|
// Creator: Dan Gisselquist, Ph.D.
|
// Gisselquist Technology, LLC
|
// Gisselquist Technology, LLC
|
//
|
//
|
////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
//
|
//
|
// Copyright (C) 2015-2018, Gisselquist Technology, LLC
|
// Copyright (C) 2015-2019, Gisselquist Technology, LLC
|
//
|
//
|
// This program is free software (firmware): you can redistribute it and/or
|
// This program is free software (firmware): you can redistribute it and/or
|
// modify it under the terms of the GNU General Public License as published
|
// modify it under the terms of the GNU General Public License as published
|
// by the Free Software Foundation, either version 3 of the License, or (at
|
// by the Free Software Foundation, either version 3 of the License, or (at
|
// your option) any later version.
|
// your option) any later version.
|
| Line 46... |
Line 46... |
//
|
//
|
module ufifo(i_clk, i_rst, i_wr, i_data, o_empty_n, i_rd, o_data, o_status, o_err);
|
module ufifo(i_clk, i_rst, i_wr, i_data, o_empty_n, i_rd, o_data, o_status, o_err);
|
parameter BW=8; // Byte/data width
|
parameter BW=8; // Byte/data width
|
parameter [3:0] LGFLEN=4;
|
parameter [3:0] LGFLEN=4;
|
parameter RXFIFO=1'b0;
|
parameter RXFIFO=1'b0;
|
parameter [0:0] F_OPT_CLK2FFLOGIC = 1'b0;
|
|
input wire i_clk, i_rst;
|
input wire i_clk, i_rst;
|
input wire i_wr;
|
input wire i_wr;
|
input wire [(BW-1):0] i_data;
|
input wire [(BW-1):0] i_data;
|
output wire o_empty_n; // True if something is in FIFO
|
output wire o_empty_n; // True if something is in FIFO
|
input wire i_rd;
|
input wire i_rd;
|
| Line 293... |
Line 292... |
// Assumptions about our input(s)
|
// Assumptions about our input(s)
|
//
|
//
|
//
|
//
|
reg f_past_valid, f_last_clk;
|
reg f_past_valid, f_last_clk;
|
|
|
initial restrict(i_rst);
|
|
|
|
generate if (F_OPT_CLK2FFLOGIC)
|
|
begin
|
|
always @($global_clock)
|
|
begin
|
|
restrict(i_clk == !f_last_clk);
|
|
f_last_clk <= i_clk;
|
|
if (!$rose(i_clk))
|
|
begin
|
|
`ASSUME($stable(i_rst));
|
|
`ASSUME($stable(i_wr));
|
|
`ASSUME($stable(i_data));
|
|
`ASSUME($stable(i_rd));
|
|
end
|
|
end
|
|
end endgenerate
|
|
|
|
//
|
//
|
// Underflows are a very real possibility, should the user wish to
|
// Underflows are a very real possibility, should the user wish to
|
// read from this FIFO while it is empty. Our parent module will need
|
// read from this FIFO while it is empty. Our parent module will need
|
// to deal with this.
|
// to deal with this.
|
//
|
//
|
