| Line 49... |
Line 49... |
output wire o_err;
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output wire o_err;
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localparam FLEN=(1<<LGFLEN);
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localparam FLEN=(1<<LGFLEN);
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reg [(BW-1):0] fifo[0:(FLEN-1)];
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reg [(BW-1):0] fifo[0:(FLEN-1)];
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reg [(LGFLEN-1):0] r_first, r_last;
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reg [(LGFLEN-1):0] r_first, r_last, r_next;
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wire [(LGFLEN-1):0] w_first_plus_one, w_first_plus_two,
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wire [(LGFLEN-1):0] w_first_plus_one, w_first_plus_two,
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w_last_plus_one;
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w_last_plus_one;
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assign w_first_plus_two = r_first + {{(LGFLEN-2){1'b0}},2'b10};
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assign w_first_plus_two = r_first + {{(LGFLEN-2){1'b0}},2'b10};
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assign w_first_plus_one = r_first + {{(LGFLEN-1){1'b0}},1'b1};
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assign w_first_plus_one = r_first + {{(LGFLEN-1){1'b0}},1'b1};
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assign w_last_plus_one = r_last + {{(LGFLEN-1){1'b0}},1'b1};
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assign w_last_plus_one = r_next; // r_last + 1'b1;
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reg will_overflow;
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reg will_overflow;
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initial will_overflow = 1'b0;
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initial will_overflow = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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| Line 118... |
Line 118... |
initial r_unfl = 1'b0;
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initial r_unfl = 1'b0;
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initial r_last = 0;
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initial r_last = 0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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begin
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begin
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r_last <= { (LGFLEN){1'b0} };
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r_last <= 0;
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r_next <= { {(LGFLEN-1){1'b0}}, 1'b1 };
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r_unfl <= 1'b0;
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r_unfl <= 1'b0;
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end else if (i_rd)
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end else if (i_rd)
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begin
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begin
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if ((i_wr)||(!will_underflow)) // (r_first != r_last)
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if ((i_wr)||(!will_underflow)) // (r_first != r_last)
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r_last <= w_last_plus_one;
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begin
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r_last <= r_next;
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r_next <= r_last +{{(LGFLEN-2){1'b0}},2'b10};
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// Last chases first
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// Last chases first
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// Need to be prepared for a possible two
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// Need to be prepared for a possible two
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// reads in quick succession
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// reads in quick succession
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// o_data <= fifo[r_last+1];
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// o_data <= fifo[r_last+1];
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else
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end else
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r_unfl <= 1'b1;
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r_unfl <= 1'b1;
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end
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end
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reg [7:0] fifo_here, fifo_next, r_data;
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reg [7:0] fifo_here, fifo_next, r_data;
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always @(posedge i_clk)
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always @(posedge i_clk)
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fifo_here <= fifo[r_last];
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fifo_here <= fifo[r_last];
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always @(posedge i_clk)
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always @(posedge i_clk)
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fifo_next <= fifo[r_last+{{(LGFLEN-1){1'b0}},1'b1}];
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fifo_next <= fifo[r_next];
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always @(posedge i_clk)
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always @(posedge i_clk)
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r_data <= i_data;
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r_data <= i_data;
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reg [1:0] osrc;
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reg [1:0] osrc;
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always @(posedge i_clk)
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always @(posedge i_clk)
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| Line 171... |
Line 174... |
reg [(LGFLEN-1):0] r_fill;
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reg [(LGFLEN-1):0] r_fill;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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r_fill <= 0;
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r_fill <= 0;
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else if ((i_rd)&&(!i_wr))
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else if ((i_rd)&&(!i_wr))
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r_fill <= r_first - r_last - 1'b1;
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r_fill <= r_first - r_next;
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else if ((!i_rd)&&(i_wr))
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else if ((!i_rd)&&(i_wr))
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r_fill <= r_first - r_last + 1'b1;
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r_fill <= r_first - r_last + 1'b1;
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else
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else
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r_fill <= r_first - r_last;
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r_fill <= r_first - r_last;
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assign o_half_full = r_fill[(LGFLEN-1)];
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assign o_half_full = r_fill[(LGFLEN-1)];
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