| Line 84... |
Line 84... |
end
|
end
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if(((i_wb_stb)&&(!i_wb_we)&&(i_wb_addr == `UART_RX_ADDR))
|
if(((i_wb_stb)&&(!i_wb_we)&&(i_wb_addr == `UART_RX_ADDR))
|
||(rx_stb))
|
||(rx_stb))
|
r_rx_data[8] <= !rx_stb;
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r_rx_data[8] <= !rx_stb;
|
assign o_cts = !r_rx_data[8];
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assign o_rts_n = r_rx_data[8];
|
assign rx_data = { 20'h00, r_rx_data };
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assign rx_data = { 20'h00, r_rx_data };
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assign rx_int = !r_rx_data[8];
|
assign rx_int = !r_rx_data[8];
|
|
|
// Transmit hardware flow control, the rts line
|
// Transmit hardware flow control, the cts line
|
wire rts;
|
wire cts_n;
|
// Set this rts value to one if you aren't ever going to use H/W flow
|
// Set this cts value to zero if you aren't ever going to use H/W flow
|
// control, otherwise set it to the value coming in from the external
|
// control, otherwise set it to the value coming in from the external
|
// i_rts pin.
|
// i_cts_n pin.
|
assign rts = i_rts;
|
assign cts_n = i_cts_n;
|
|
|
//
|
//
|
// Then the UART transmitter
|
// Then the UART transmitter
|
//
|
//
|
//
|
//
|
| Line 107... |
Line 107... |
reg [7:0] r_tx_data;
|
reg [7:0] r_tx_data;
|
reg r_tx_stb, r_tx_break;
|
reg r_tx_stb, r_tx_break;
|
wire [31:0] tx_data;
|
wire [31:0] tx_data;
|
txuart #(UART_SETUP) tx(i_clk, 1'b0, uart_setup,
|
txuart #(UART_SETUP) tx(i_clk, 1'b0, uart_setup,
|
r_tx_break, r_tx_stb, r_tx_data,
|
r_tx_break, r_tx_stb, r_tx_data,
|
rts, o_tx, tx_busy);
|
cts_n, o_tx, tx_busy);
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((i_wb_stb)&&(i_wb_addr == 5'h0f))
|
if ((i_wb_stb)&&(i_wb_addr == 5'h0f))
|
begin
|
begin
|
r_tx_stb <= (!r_tx_break)&&(!i_wb_data[8]);
|
r_tx_stb <= (!r_tx_break)&&(!i_wb_data[8]);
|
r_tx_data <= i_wb_data[7:0];
|
r_tx_data <= i_wb_data[7:0];
|
| Line 119... |
Line 119... |
end else if (!tx_busy)
|
end else if (!tx_busy)
|
begin
|
begin
|
r_tx_stb <= 1'b0;
|
r_tx_stb <= 1'b0;
|
r_tx_data <= 8'h0;
|
r_tx_data <= 8'h0;
|
end
|
end
|
assign tx_data = { 16'h00, rts, 3'h0,
|
assign tx_data = { 16'h00, cts_n, 3'h0,
|
ck_uart, o_tx, r_tx_break, tx_busy,
|
ck_uart, o_tx, r_tx_break, tx_busy,
|
r_tx_data };
|
r_tx_data };
|
assign tx_int = ~tx_busy;
|
assign tx_int = ~tx_busy;
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
