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[/] [wbuart32/] [trunk/] [rtl/] [wbuart-insert.v] - Diff between revs 2 and 5

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Rev 2 Rev 5
Line 60... Line 60...
        //
        //
        // First the UART receiver
        // First the UART receiver
        //
        //
        wire    rx_stb, rx_break, rx_perr, rx_ferr, ck_uart;
        wire    rx_stb, rx_break, rx_perr, rx_ferr, ck_uart;
        wire    [7:0]    rx_data_port;
        wire    [7:0]    rx_data_port;
        rxuart  rx(i_clk, 1'b0, uart_setup, i_rx,
        rxuart  #(UART_SETUP) rx(i_clk, 1'b0, uart_setup, i_rx,
                        rx_stb, rx_data_port, rx_break,
                        rx_stb, rx_data_port, rx_break,
                        rx_perr, rx_ferr, ck_uart);
                        rx_perr, rx_ferr, ck_uart);
 
 
        wire    [31:0]   rx_data;
        wire    [31:0]   rx_data;
        reg     [11:0]   r_rx_data;
        reg     [11:0]   r_rx_data;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (rx_stb)
                if (rx_stb)
                begin
                begin
                        r_rx_data[11] <= rx_break;
                        r_rx_data[11] <= (r_rx_data[11])||(rx_break);
                        r_rx_data[10] <= rx_ferr;
                        r_rx_data[10] <= (r_rx_data[10])||(rx_ferr);
                        r_rx_data[ 9] <= rx_perr;
                        r_rx_data[ 9] <= (r_rx_data[ 9])||(rx_perr);
                        r_rx_data[7:0]<= rx_data_port;
                        r_rx_data[7:0]<= rx_data_port;
 
                end else if ((i_wb_stb)&&(i_wb_we)
 
                                        &&(i_wb_addr == `UART_RX_ADDR))
 
                begin
 
                        r_rx_data[11] <= (rx_break)&& (!i_wb_data[11]);
 
                        r_rx_data[10] <= (rx_ferr) && (!i_wb_data[10]);
 
                        r_rx_data[ 9] <= (rx_perr) && (!i_wb_data[ 9]);
                end
                end
        always @(posedge i_clk)
        always @(posedge i_clk)
                if(((i_wb_stb)&&(~i_wb_we)&&(i_wb_addr == `UART_RX_ADDR))
                if(((i_wb_stb)&&(~i_wb_we)&&(i_wb_addr == `UART_RX_ADDR))
                                ||(rx_stb))
                                ||(rx_stb))
                        r_rx_data[8] <= !rx_stb;
                        r_rx_data[8] <= !rx_stb;
        assign  o_cts = rx_stb;
        assign  o_cts = !r_rx_data[8];
        assign  rx_data = { 20'h00, r_rx_data };
        assign  rx_data = { 20'h00, r_rx_data };
        assign  rx_int = r_rx_data[8];
        assign  rx_int = !r_rx_data[8];
 
 
        //
        //
        // Then the UART transmitter
        // Then the UART transmitter
        //
        //
        wire    tx_busy;
        wire    tx_busy;
        reg     [7:0]    r_tx_data;
        reg     [7:0]    r_tx_data;
        reg             r_tx_stb, r_tx_break;
        reg             r_tx_stb, r_tx_break;
        wire    [31:0]   tx_data;
        wire    [31:0]   tx_data;
        txuart  tx(i_clk, 1'b0, uart_setup,
        txuart  #(UART_SETUP) tx(i_clk, 1'b0, uart_setup,
                        r_tx_break, r_tx_stb, r_tx_data,
                        r_tx_break, r_tx_stb, r_tx_data,
                        o_tx, tx_busy);
                        o_tx, tx_busy);
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((i_wb_stb)&&(i_wb_addr == 5'h0f))
                if ((i_wb_stb)&&(i_wb_addr == 5'h0f))
                begin
                begin

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