| Line 48... |
Line 48... |
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// Ideally, UART_SETUP is defined somewhere. I commonly like to define
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// Ideally, UART_SETUP is defined somewhere. I commonly like to define
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// it to CLKRATE / BAUDRATE, to give me 8N1 performance. 4MB is useful
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// it to CLKRATE / BAUDRATE, to give me 8N1 performance. 4MB is useful
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// to me, so 100MHz / 4M = 25 could be the setup. You can also use
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// to me, so 100MHz / 4M = 25 could be the setup. You can also use
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// 200MHz / 4MB = 50 ... it all depends upon your clock.
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// 200MHz / 4MB = 50 ... it all depends upon your clock.
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`define UART_SETUP 30'd25
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`define UART_SETUP 31'd25
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reg [29:0] uart_setup;
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reg [30:0] uart_setup;
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initial uart_setup = `UART_SETUP;
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initial uart_setup = `UART_SETUP;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((i_wb_stb)&&(i_wb_addr == `UART_SETUP_ADDR))
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if ((i_wb_stb)&&(i_wb_addr == `UART_SETUP_ADDR))
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uart_setup[29:0] <= i_wb_data[29:0];
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uart_setup[30:0] <= i_wb_data[30:0];
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//
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//
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// First the UART receiver
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// First the UART receiver
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//
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//
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wire rx_stb, rx_break, rx_perr, rx_ferr, ck_uart;
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wire rx_stb, rx_break, rx_perr, rx_ferr, ck_uart;
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| Line 81... |
Line 81... |
r_rx_data[11] <= (rx_break)&& (!i_wb_data[11]);
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r_rx_data[11] <= (rx_break)&& (!i_wb_data[11]);
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r_rx_data[10] <= (rx_ferr) && (!i_wb_data[10]);
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r_rx_data[10] <= (rx_ferr) && (!i_wb_data[10]);
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r_rx_data[ 9] <= (rx_perr) && (!i_wb_data[ 9]);
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r_rx_data[ 9] <= (rx_perr) && (!i_wb_data[ 9]);
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end
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end
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always @(posedge i_clk)
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always @(posedge i_clk)
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if(((i_wb_stb)&&(~i_wb_we)&&(i_wb_addr == `UART_RX_ADDR))
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if(((i_wb_stb)&&(!i_wb_we)&&(i_wb_addr == `UART_RX_ADDR))
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||(rx_stb))
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||(rx_stb))
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r_rx_data[8] <= !rx_stb;
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r_rx_data[8] <= !rx_stb;
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assign o_cts = !r_rx_data[8];
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assign o_cts = !r_rx_data[8];
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assign rx_data = { 20'h00, r_rx_data };
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assign rx_data = { 20'h00, r_rx_data };
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assign rx_int = !r_rx_data[8];
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assign rx_int = !r_rx_data[8];
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// Transmit hardware flow control, the rts line
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wire rts;
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// Set this rts value to one if you aren't ever going to use H/W flow
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// control, otherwise set it to the value coming in from the external
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// i_rts pin.
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assign rts = i_rts;
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//
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//
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// Then the UART transmitter
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// Then the UART transmitter
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//
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//
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//
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//
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// Now onto the transmitter itself
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wire tx_busy;
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wire tx_busy;
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reg [7:0] r_tx_data;
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reg [7:0] r_tx_data;
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reg r_tx_stb, r_tx_break;
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reg r_tx_stb, r_tx_break;
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wire [31:0] tx_data;
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wire [31:0] tx_data;
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txuart #(UART_SETUP) tx(i_clk, 1'b0, uart_setup,
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txuart #(UART_SETUP) tx(i_clk, 1'b0, uart_setup,
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r_tx_break, r_tx_stb, r_tx_data,
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r_tx_break, r_tx_stb, r_tx_data,
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o_tx, tx_busy);
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rts, o_tx, tx_busy);
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((i_wb_stb)&&(i_wb_addr == 5'h0f))
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if ((i_wb_stb)&&(i_wb_addr == 5'h0f))
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begin
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begin
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r_tx_stb <= (!r_tx_break)&&(!i_wb_data[8]);
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r_tx_stb <= (!r_tx_break)&&(!i_wb_data[8]);
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r_tx_data <= i_wb_data[7:0];
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r_tx_data <= i_wb_data[7:0];
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r_tx_break<= i_wb_data[9];
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r_tx_break<= i_wb_data[9];
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end else if (~tx_busy)
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end else if (!tx_busy)
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begin
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begin
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r_tx_stb <= 1'b0;
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r_tx_stb <= 1'b0;
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r_tx_data <= 8'h0;
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r_tx_data <= 8'h0;
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end
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end
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assign tx_data = { 20'h00,
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assign tx_data = { 16'h00, rts, 3'h0,
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ck_uart, o_tx, r_tx_break, tx_busy,
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ck_uart, o_tx, r_tx_break, tx_busy,
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r_tx_data };
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r_tx_data };
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assign tx_int = ~tx_busy;
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assign tx_int = ~tx_busy;
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always @(posedge i_clk)
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always @(posedge i_clk)
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case(i_wb_addr)
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case(i_wb_addr)
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`UART_SETUP_ADDR: o_wb_data <= { 2'b00, uart_setup };
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`UART_SETUP_ADDR: o_wb_data <= { 1'b0, uart_setup };
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`UART_RX_ADDR : o_wb_data <= rx_data;
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`UART_RX_ADDR : o_wb_data <= rx_data;
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`UART_TX_ADDR : o_wb_data <= tx_data;
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`UART_TX_ADDR : o_wb_data <= tx_data;
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//
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//
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// The rest of these address slots are left open here for
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// The rest of these address slots are left open here for
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// whatever else you might wish to connect to this bus/STB
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// whatever else you might wish to connect to this bus/STB
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