| Line 36... |
Line 36... |
//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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`default_nettype none
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//
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`define UART_SETUP 2'b00
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`define UART_SETUP 2'b00
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`define UART_FIFO 2'b01
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`define UART_FIFO 2'b01
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`define UART_RXREG 2'b10
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`define UART_RXREG 2'b10
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`define UART_TXREG 2'b11
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`define UART_TXREG 2'b11
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module wbuart(i_clk, i_rst,
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module wbuart(i_clk, i_rst,
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| Line 58... |
Line 60... |
// sure its within the bounds we can support with our current
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// sure its within the bounds we can support with our current
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// interface.
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// interface.
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localparam [3:0] LCLLGFLEN = (LGFLEN > 4'ha)? 4'ha
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localparam [3:0] LCLLGFLEN = (LGFLEN > 4'ha)? 4'ha
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: ((LGFLEN < 4'h2) ? 4'h2 : LGFLEN);
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: ((LGFLEN < 4'h2) ? 4'h2 : LGFLEN);
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//
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//
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input i_clk, i_rst;
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input wire i_clk, i_rst;
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// Wishbone inputs
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// Wishbone inputs
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input wire i_wb_cyc, i_wb_stb, i_wb_we;
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input [1:0] i_wb_addr;
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input wire [1:0] i_wb_addr;
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input [31:0] i_wb_data;
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input wire [31:0] i_wb_data;
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output reg o_wb_ack;
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output reg o_wb_ack;
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output wire o_wb_stall;
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output wire o_wb_stall;
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output reg [31:0] o_wb_data;
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output reg [31:0] o_wb_data;
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//
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//
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input i_uart_rx;
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input wire i_uart_rx;
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output wire o_uart_tx;
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output wire o_uart_tx;
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// RTS is used for hardware flow control. According to Wikipedia, it
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// RTS is used for hardware flow control. According to Wikipedia, it
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// should probably be renamed RTR for "ready to receive". It tell us
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// should probably be renamed RTR for "ready to receive". It tell us
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// whether or not the receiving hardware is ready to accept another
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// whether or not the receiving hardware is ready to accept another
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// byte. If low, the transmitter will pause.
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// byte. If low, the transmitter will pause.
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//
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//
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// If you don't wish to use hardware flow control, just set i_cts_n to
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// If you don't wish to use hardware flow control, just set i_cts_n to
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// 1'b0 and let the optimizer simply remove this logic.
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// 1'b0 and let the optimizer simply remove this logic.
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input i_cts_n;
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input wire i_cts_n;
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// CTS is the "Clear-to-send" signal. We set it anytime our FIFO
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// CTS is the "Clear-to-send" signal. We set it anytime our FIFO
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// isn't full. Feel free to ignore this output if you do not wish to
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// isn't full. Feel free to ignore this output if you do not wish to
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// use flow control.
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// use flow control.
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output reg o_rts_n;
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output reg o_rts_n;
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output wire o_uart_rx_int, o_uart_tx_int,
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output wire o_uart_rx_int, o_uart_tx_int,
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Line 340... |
tx_uart_reset <= i_wb_data[12];
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tx_uart_reset <= i_wb_data[12];
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else
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else
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tx_uart_reset <= 1'b0;
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tx_uart_reset <= 1'b0;
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`ifdef USE_LITE_UART
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`ifdef USE_LITE_UART
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txuart #(INITIAL_SETUP[23:0]) tx(i_clk, (tx_empty_n), tx_data,
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txuartlite #(INITIAL_SETUP[23:0]) tx(i_clk, (tx_empty_n), tx_data,
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o_uart_tx, tx_busy);
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o_uart_tx, tx_busy);
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`else
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`else
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wire cts_n;
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wire cts_n;
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assign cts_n = (HARDWARE_FLOW_CONTROL_PRESENT)&&(i_cts_n);
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assign cts_n = (HARDWARE_FLOW_CONTROL_PRESENT)&&(i_cts_n);
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// Finally, the UART transmitter module itself. Note that we haven't
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// Finally, the UART transmitter module itself. Note that we haven't
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