| Line 62... |
Line 62... |
localparam [3:0] LCLLGFLEN = (LGFLEN > 4'ha)? 4'ha
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localparam [3:0] LCLLGFLEN = (LGFLEN > 4'ha)? 4'ha
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: ((LGFLEN < 4'h2) ? 4'h2 : LGFLEN);
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: ((LGFLEN < 4'h2) ? 4'h2 : LGFLEN);
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//
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//
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input wire i_clk, i_rst;
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input wire i_clk, i_rst;
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// Wishbone inputs
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// Wishbone inputs
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input wire i_wb_cyc, i_wb_stb, i_wb_we;
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input wire i_wb_cyc; // We ignore CYC for efficiency
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input wire i_wb_stb, i_wb_we;
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input wire [1:0] i_wb_addr;
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input wire [1:0] i_wb_addr;
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input wire [31:0] i_wb_data;
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input wire [31:0] i_wb_data; // and only use 30 lines here
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output reg o_wb_ack;
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output reg o_wb_ack;
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output wire o_wb_stall;
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output wire o_wb_stall;
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output reg [31:0] o_wb_data;
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output reg [31:0] o_wb_data;
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//
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//
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input wire i_uart_rx;
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input wire i_uart_rx;
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| Line 93... |
Line 94... |
//
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//
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// The UART setup parameters: bits per byte, stop bits, parity, and
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// The UART setup parameters: bits per byte, stop bits, parity, and
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// baud rate are all captured within this uart_setup register.
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// baud rate are all captured within this uart_setup register.
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//
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//
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reg [30:0] uart_setup;
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reg [30:0] uart_setup;
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initial uart_setup = INITIAL_SETUP;
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initial uart_setup = INITIAL_SETUP
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| ((HARDWARE_FLOW_CONTROL_PRESENT==1'b0)? 31'h40000000 : 0);
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always @(posedge i_clk)
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always @(posedge i_clk)
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// Under wishbone rules, a write takes place any time i_wb_stb
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// Under wishbone rules, a write takes place any time i_wb_stb
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// is high. If that's the case, and if the write was to the
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// is high. If that's the case, and if the write was to the
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// setup address, then set us up for the new parameters.
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// setup address, then set us up for the new parameters.
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if ((i_wb_stb)&&(i_wb_addr == `UART_SETUP)&&(i_wb_we))
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if ((i_wb_stb)&&(i_wb_addr == `UART_SETUP)&&(i_wb_we))
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| Line 178... |
Line 180... |
// The clear to send line, which may be ignored, but which we set here
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// The clear to send line, which may be ignored, but which we set here
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// to be true any time the FIFO has fewer than N-2 items in it.
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// to be true any time the FIFO has fewer than N-2 items in it.
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// Why N-1? Because at N-1 we are totally full, but already so full
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// Why N-1? Because at N-1 we are totally full, but already so full
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// that if the transmit end starts sending we won't have a location to
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// that if the transmit end starts sending we won't have a location to
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// receive it. (Transmit might've started on the next character by the
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// receive it. (Transmit might've started on the next character by the
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// time we set this--need to set it to one character before necessary
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// time we set this--thus we need to set it to one, one character before
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// necessary).
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wire [(LCLLGFLEN-1):0] check_cutoff;
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assign check_cutoff = -3;
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_rts_n = ((HARDWARE_FLOW_CONTROL_PRESENT)
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o_rts_n <= ((HARDWARE_FLOW_CONTROL_PRESENT)
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&&(!uart_setup[30])
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&&(!uart_setup[30])
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&&(rxf_status[(LCLLGFLEN+1):4]=={(LCLLGFLEN-2){1'b1}}));
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&&(rxf_status[(LCLLGFLEN+1):2] > check_cutoff));
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// If the bus requests that we read from the receive FIFO, we need to
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// If the bus requests that we read from the receive FIFO, we need to
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// tell this to the receive FIFO. Note that because we are using a
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// tell this to the receive FIFO. Note that because we are using a
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// clock here, the output from the receive FIFO will necessarily be
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// clock here, the output from the receive FIFO will necessarily be
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// delayed by an extra clock.
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// delayed by an extra clock.
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| Line 416... |
Line 421... |
// pipelined, and nothing stalls that pipeline. (Creates FIFO errors,
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// pipelined, and nothing stalls that pipeline. (Creates FIFO errors,
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// perhaps, but doesn't stall the pipeline.) Hence, we can just
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// perhaps, but doesn't stall the pipeline.) Hence, we can just
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// set this value to zero.
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// set this value to zero.
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assign o_wb_stall = 1'b0;
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assign o_wb_stall = 1'b0;
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// Make verilator happy
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// verilator lint_off UNUSED
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wire [33:0] unused;
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assign unused = { i_rst, i_wb_cyc, i_wb_data };
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// verilator lint_on UNUSED
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endmodule
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endmodule
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No newline at end of file
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