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[/] [wbuart32/] [trunk/] [rtl/] [wbuart.v] - Diff between revs 18 and 21
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| Rev 18 |
Rev 21 |
| Line 177... |
Line 177... |
// the CPU.
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// the CPU.
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assign o_uart_rx_int = rxf_status[0];
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assign o_uart_rx_int = rxf_status[0];
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// The clear to send line, which may be ignored, but which we set here
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// The clear to send line, which may be ignored, but which we set here
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// to be true any time the FIFO has fewer than N-2 items in it.
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// to be true any time the FIFO has fewer than N-2 items in it.
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// Why N-1? Because at N-1 we are totally full, but already so full
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// Why not N-1? Because at N-1 we are totally full, but already so full
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// that if the transmit end starts sending we won't have a location to
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// that if the transmit end starts sending we won't have a location to
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// receive it. (Transmit might've started on the next character by the
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// receive it. (Transmit might've started on the next character by the
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// time we set this--thus we need to set it to one, one character before
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// time we set this--thus we need to set it to one, one character before
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// necessary).
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// necessary).
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wire [(LCLLGFLEN-1):0] check_cutoff;
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wire [(LCLLGFLEN-1):0] check_cutoff;
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