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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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// Copyright (C) 2015-2019, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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//
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//
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`define UART_SETUP 2'b00
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`define UART_SETUP 2'b00
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`define UART_FIFO 2'b01
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`define UART_FIFO 2'b01
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`define UART_RXREG 2'b10
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`define UART_RXREG 2'b10
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`define UART_TXREG 2'b11
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`define UART_TXREG 2'b11
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//
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// `define USE_LITE_UART
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module wbuart(i_clk, i_rst,
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module wbuart(i_clk, i_rst,
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//
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//
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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//
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//
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// the UART input, a clock, and a reset line, and produces outputs:
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// the UART input, a clock, and a reset line, and produces outputs:
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// a stb (true when new data is ready), and an 8-bit data out value
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// a stb (true when new data is ready), and an 8-bit data out value
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// valid when stb is high.
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// valid when stb is high.
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`ifdef USE_LITE_UART
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`ifdef USE_LITE_UART
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rxuartlite #(INITIAL_SETUP[23:0])
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rxuartlite #(INITIAL_SETUP[23:0])
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rx(i_clk, (i_rst), i_uart_rx, rx_stb, rx_uart_data);
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rx(i_clk, i_uart_rx, rx_stb, rx_uart_data);
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assign rx_break = 1'b0;
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assign rx_break = 1'b0;
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assign rx_perr = 1'b0;
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assign rx_perr = 1'b0;
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assign rx_ferr = 1'b0;
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assign rx_ferr = 1'b0;
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assign ck_uart = 1'b0;
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assign ck_uart = 1'b0;
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`else
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`else
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