//=======================================================================
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//=======================================================================
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// Project Monophony
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// Project Monophony
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// Wire-Frame 3D Graphics Accelerator IP Core
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// Wire-Frame 3D Graphics Accelerator IP Core
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//
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//
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// File:
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// File:
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// fm_axi_s.v
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// fm_axi_s.v
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//
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//
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// Abstract:
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// Abstract:
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// AXI Slave interface bridge
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// AXI Slave interface bridge
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//
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//
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// Author:
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// Author:
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// Kenji Ishimaru (info.wf3d@gmail.com)
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// Kenji Ishimaru (info.info.wf3d@gmail.com)
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//
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//
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//======================================================================
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//======================================================================
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//
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//
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// Copyright (c) 2016, Kenji Ishimaru
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// Copyright (c) 2016, Kenji Ishimaru
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// All rights reserved.
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// All rights reserved.
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// modification, are permitted provided that the following conditions are met:
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//
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//
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// -Redistributions of source code must retain the above copyright notice,
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// -Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// this list of conditions and the following disclaimer.
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// -Redistributions in binary form must reproduce the above copyright notice,
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// -Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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// and/or other materials provided with the distribution.
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//
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//
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// Revision History
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// Revision History
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module fm_axi_s (
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module fm_axi_s (
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// system
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// system
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clk_core,
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clk_core,
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rst_x,
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rst_x,
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// AXI write port
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// AXI write port
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i_awid_s,
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i_awid_s,
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i_awaddr_s,
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i_awaddr_s,
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i_awlen_s,
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i_awlen_s,
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i_awsize_s,
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i_awsize_s,
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i_awburst_s,
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i_awburst_s,
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i_awlock_s,
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i_awlock_s,
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i_awcache_s,
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i_awcache_s,
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i_awprot_s,
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i_awprot_s,
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i_awvalid_s,
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i_awvalid_s,
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o_awready_s,
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o_awready_s,
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i_wid_s,
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i_wid_s,
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i_wdata_s,
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i_wdata_s,
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i_wstrb_s,
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i_wstrb_s,
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i_wlast_s,
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i_wlast_s,
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i_wvalid_s,
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i_wvalid_s,
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o_wready_s,
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o_wready_s,
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o_bid_s,
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o_bid_s,
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o_bresp_s,
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o_bresp_s,
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o_bvalid_s,
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o_bvalid_s,
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i_bready_s,
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i_bready_s,
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// AXI read port
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// AXI read port
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i_arid_s,
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i_arid_s,
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i_araddr_s,
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i_araddr_s,
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i_arlen_s,
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i_arlen_s,
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i_arsize_s,
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i_arsize_s,
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i_arburst_s,
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i_arburst_s,
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i_arlock_s,
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i_arlock_s,
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i_arcache_s,
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i_arcache_s,
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i_arprot_s,
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i_arprot_s,
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i_arvalid_s,
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i_arvalid_s,
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o_arready_s,
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o_arready_s,
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o_rid_s,
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o_rid_s,
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o_rdata_s,
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o_rdata_s,
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o_rresp_s,
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o_rresp_s,
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o_rlast_s,
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o_rlast_s,
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o_rvalid_s,
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o_rvalid_s,
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i_rready_s,
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i_rready_s,
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// internal bus
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// internal bus
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o_req,
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o_req,
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o_wr,
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o_wr,
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o_adrs,
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o_adrs,
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i_ack,
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i_ack,
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o_be,
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o_be,
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o_wd,
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o_wd,
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i_rstr,
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i_rstr,
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i_rd
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i_rd
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);
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);
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`include "polyphony_axi_def.v"
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`include "polyphony_axi_def.v"
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//////////////////////////////////
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//////////////////////////////////
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// I/O port definition
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// I/O port definition
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//////////////////////////////////
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//////////////////////////////////
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// system
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// system
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input clk_core;
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input clk_core;
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input rst_x;
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input rst_x;
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// AXI Slave
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// AXI Slave
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// write port
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// write port
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input [P_AXI_S_AWID-1:0] i_awid_s;
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input [P_AXI_S_AWID-1:0] i_awid_s;
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input [P_AXI_S_AWADDR-1:0] i_awaddr_s;
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input [P_AXI_S_AWADDR-1:0] i_awaddr_s;
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input [P_AXI_S_AWLEN-1:0] i_awlen_s;
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input [P_AXI_S_AWLEN-1:0] i_awlen_s;
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input [P_AXI_S_AWSIZE-1:0] i_awsize_s;
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input [P_AXI_S_AWSIZE-1:0] i_awsize_s;
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input [P_AXI_S_AWBURST-1:0] i_awburst_s;
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input [P_AXI_S_AWBURST-1:0] i_awburst_s;
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input [P_AXI_S_AWLOCK-1:0] i_awlock_s;
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input [P_AXI_S_AWLOCK-1:0] i_awlock_s;
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input [P_AXI_S_AWCACHE-1:0] i_awcache_s;
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input [P_AXI_S_AWCACHE-1:0] i_awcache_s;
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input [P_AXI_S_AWPROT-1:0] i_awprot_s;
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input [P_AXI_S_AWPROT-1:0] i_awprot_s;
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input i_awvalid_s;
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input i_awvalid_s;
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output o_awready_s;
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output o_awready_s;
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input [P_AXI_S_WID-1:0] i_wid_s;
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input [P_AXI_S_WID-1:0] i_wid_s;
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input [P_AXI_S_WDATA-1:0] i_wdata_s;
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input [P_AXI_S_WDATA-1:0] i_wdata_s;
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input [P_AXI_S_WSTRB-1:0] i_wstrb_s;
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input [P_AXI_S_WSTRB-1:0] i_wstrb_s;
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input i_wlast_s;
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input i_wlast_s;
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input i_wvalid_s;
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input i_wvalid_s;
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output o_wready_s;
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output o_wready_s;
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output [P_AXI_S_BID-1:0] o_bid_s;
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output [P_AXI_S_BID-1:0] o_bid_s;
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output [P_AXI_S_BRESP-1:0] o_bresp_s;
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output [P_AXI_S_BRESP-1:0] o_bresp_s;
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output o_bvalid_s;
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output o_bvalid_s;
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input i_bready_s;
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input i_bready_s;
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// read port
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// read port
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input [P_AXI_S_ARID-1:0] i_arid_s;
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input [P_AXI_S_ARID-1:0] i_arid_s;
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input [P_AXI_S_ARADDR-1:0] i_araddr_s;
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input [P_AXI_S_ARADDR-1:0] i_araddr_s;
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input [P_AXI_S_ARLEN-1:0] i_arlen_s;
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input [P_AXI_S_ARLEN-1:0] i_arlen_s;
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input [P_AXI_S_ARSIZE-1:0] i_arsize_s;
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input [P_AXI_S_ARSIZE-1:0] i_arsize_s;
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input [P_AXI_S_ARBURST-1:0] i_arburst_s;
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input [P_AXI_S_ARBURST-1:0] i_arburst_s;
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input [P_AXI_S_ARLOCK-1:0] i_arlock_s;
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input [P_AXI_S_ARLOCK-1:0] i_arlock_s;
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input [P_AXI_S_ARCACHE-1:0] i_arcache_s;
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input [P_AXI_S_ARCACHE-1:0] i_arcache_s;
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input [P_AXI_S_ARPROT-1:0] i_arprot_s;
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input [P_AXI_S_ARPROT-1:0] i_arprot_s;
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input i_arvalid_s;
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input i_arvalid_s;
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output o_arready_s;
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output o_arready_s;
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// read response
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// read response
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output [P_AXI_S_RID-1:0] o_rid_s;
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output [P_AXI_S_RID-1:0] o_rid_s;
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output [P_AXI_S_RDATA-1:0] o_rdata_s;
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output [P_AXI_S_RDATA-1:0] o_rdata_s;
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output [P_AXI_S_RRESP-1:0] o_rresp_s;
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output [P_AXI_S_RRESP-1:0] o_rresp_s;
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output o_rlast_s;
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output o_rlast_s;
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output o_rvalid_s;
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output o_rvalid_s;
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input i_rready_s;
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input i_rready_s;
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// internal side
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// internal side
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output o_req;
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output o_req;
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output o_wr;
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output o_wr;
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output [23:0] o_adrs;
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output [23:0] o_adrs;
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input i_ack;
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input i_ack;
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output [3:0] o_be;
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output [3:0] o_be;
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output [31:0] o_wd;
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output [31:0] o_wd;
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input i_rstr;
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input i_rstr;
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input [31:0] i_rd;
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input [31:0] i_rd;
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//////////////////////////////////
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//////////////////////////////////
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// parameter definition
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// parameter definition
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//////////////////////////////////
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//////////////////////////////////
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localparam P_IDLE = 'd0;
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localparam P_IDLE = 'd0;
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localparam P_WRITE_CMD = 'd1;
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localparam P_WRITE_CMD = 'd1;
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localparam P_READ_CMD = 'd2;
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localparam P_READ_CMD = 'd2;
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localparam P_READ_DT = 'd3;
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localparam P_READ_DT = 'd3;
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localparam P_WC_FIFO_W = P_AXI_S_AWID +
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localparam P_WC_FIFO_W = P_AXI_S_AWID +
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P_AXI_S_AWADDR +
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P_AXI_S_AWADDR +
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P_AXI_S_AWLEN +
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P_AXI_S_AWLEN +
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P_AXI_S_AWSIZE +
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P_AXI_S_AWSIZE +
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P_AXI_S_AWBURST +
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P_AXI_S_AWBURST +
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P_AXI_S_AWLOCK +
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P_AXI_S_AWLOCK +
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P_AXI_S_AWCACHE +
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P_AXI_S_AWCACHE +
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P_AXI_S_AWPROT;
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P_AXI_S_AWPROT;
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localparam P_WD_FIFO_W = P_AXI_S_WID +
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localparam P_WD_FIFO_W = P_AXI_S_WID +
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P_AXI_S_WDATA +
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P_AXI_S_WDATA +
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P_AXI_S_WSTRB + 1;
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P_AXI_S_WSTRB + 1;
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localparam P_WR_FIFO_W = P_AXI_S_BID +
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localparam P_WR_FIFO_W = P_AXI_S_BID +
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P_AXI_S_BRESP;
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P_AXI_S_BRESP;
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localparam P_RC_FIFO_W = P_AXI_S_ARID +
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localparam P_RC_FIFO_W = P_AXI_S_ARID +
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P_AXI_S_ARADDR +
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P_AXI_S_ARADDR +
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P_AXI_S_ARLEN +
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P_AXI_S_ARLEN +
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P_AXI_S_ARSIZE +
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P_AXI_S_ARSIZE +
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P_AXI_S_ARBURST +
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P_AXI_S_ARBURST +
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P_AXI_S_ARLOCK +
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P_AXI_S_ARLOCK +
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P_AXI_S_ARCACHE +
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P_AXI_S_ARCACHE +
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P_AXI_S_ARPROT;
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P_AXI_S_ARPROT;
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localparam P_RR_FIFO_W = P_AXI_S_RID +
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localparam P_RR_FIFO_W = P_AXI_S_RID +
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P_AXI_S_RDATA +
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P_AXI_S_RDATA +
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P_AXI_S_RRESP + 1;
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P_AXI_S_RRESP + 1;
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//////////////////////////////////
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//////////////////////////////////
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// reg
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// reg
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//////////////////////////////////
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//////////////////////////////////
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reg [1:0] r_state;
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reg [1:0] r_state;
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reg [P_AXI_S_ARID-1:0] r_arid_s;
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reg [P_AXI_S_ARID-1:0] r_arid_s;
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//////////////////////////////////
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//////////////////////////////////
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// wire
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// wire
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//////////////////////////////////
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//////////////////////////////////
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wire w_w_access;
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wire w_w_access;
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wire w_r_access;
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wire w_r_access;
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// write command
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// write command
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wire [P_AXI_S_AWID-1:0] w_awid_s;
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wire [P_AXI_S_AWID-1:0] w_awid_s;
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wire [P_AXI_S_AWADDR-1:0] w_awaddr_s;
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wire [P_AXI_S_AWADDR-1:0] w_awaddr_s;
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wire [P_AXI_S_AWLEN-1:0] w_awlen_s;
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wire [P_AXI_S_AWLEN-1:0] w_awlen_s;
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wire [P_AXI_S_AWSIZE-1:0] w_awsize_s;
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wire [P_AXI_S_AWSIZE-1:0] w_awsize_s;
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wire [P_AXI_S_AWBURST-1:0] w_awburst_s;
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wire [P_AXI_S_AWBURST-1:0] w_awburst_s;
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wire [P_AXI_S_AWLOCK-1:0] w_awlock_s;
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wire [P_AXI_S_AWLOCK-1:0] w_awlock_s;
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wire [P_AXI_S_AWCACHE-1:0] w_awcache_s;
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wire [P_AXI_S_AWCACHE-1:0] w_awcache_s;
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wire [P_AXI_S_AWPROT-1:0] w_awprot_s;
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wire [P_AXI_S_AWPROT-1:0] w_awprot_s;
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wire [P_WC_FIFO_W-1:0] w_wc_fifo_in;
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wire [P_WC_FIFO_W-1:0] w_wc_fifo_in;
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wire [P_WC_FIFO_W-1:0] w_wc_fifo_out;
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wire [P_WC_FIFO_W-1:0] w_wc_fifo_out;
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wire w_wc_full;
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wire w_wc_full;
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wire w_wc_empty;
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wire w_wc_empty;
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wire w_wc_ren;
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wire w_wc_ren;
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// write data
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// write data
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wire [P_AXI_S_WID-1:0] w_wid_s;
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wire [P_AXI_S_WID-1:0] w_wid_s;
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wire [P_AXI_S_WDATA-1:0] w_wdata_s;
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wire [P_AXI_S_WDATA-1:0] w_wdata_s;
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wire [P_AXI_S_WSTRB-1:0] w_wstrb_s;
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wire [P_AXI_S_WSTRB-1:0] w_wstrb_s;
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wire w_wlast_s;
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wire w_wlast_s;
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wire [P_WD_FIFO_W-1:0] w_wd_fifo_in;
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wire [P_WD_FIFO_W-1:0] w_wd_fifo_in;
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wire [P_WD_FIFO_W-1:0] w_wd_fifo_out;
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wire [P_WD_FIFO_W-1:0] w_wd_fifo_out;
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wire w_wd_full;
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wire w_wd_full;
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wire w_wd_empty;
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wire w_wd_empty;
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wire w_wd_ren;
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wire w_wd_ren;
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// write response
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// write response
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wire [P_AXI_S_BID-1:0] w_bid_s;
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wire [P_AXI_S_BID-1:0] w_bid_s;
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wire [P_AXI_S_BRESP-1:0] w_bresp_s;
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wire [P_AXI_S_BRESP-1:0] w_bresp_s;
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wire [P_WR_FIFO_W-1:0] w_wr_fifo_in;
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wire [P_WR_FIFO_W-1:0] w_wr_fifo_in;
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wire [P_WR_FIFO_W-1:0] w_wr_fifo_out;
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wire [P_WR_FIFO_W-1:0] w_wr_fifo_out;
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wire w_wr_full;
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wire w_wr_full;
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wire w_wr_empty;
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wire w_wr_empty;
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wire w_wr_ren;
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wire w_wr_ren;
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// read command
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// read command
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wire [P_AXI_S_ARID-1:0] w_arid_s;
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wire [P_AXI_S_ARID-1:0] w_arid_s;
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wire [P_AXI_S_ARADDR-1:0] w_araddr_s;
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wire [P_AXI_S_ARADDR-1:0] w_araddr_s;
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wire [P_AXI_S_ARLEN-1:0] w_arlen_s;
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wire [P_AXI_S_ARLEN-1:0] w_arlen_s;
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wire [P_AXI_S_ARSIZE-1:0] w_arsize_s;
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wire [P_AXI_S_ARSIZE-1:0] w_arsize_s;
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wire [P_AXI_S_ARBURST-1:0] w_arburst_s;
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wire [P_AXI_S_ARBURST-1:0] w_arburst_s;
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wire [P_AXI_S_ARLOCK-1:0] w_arlock_s;
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wire [P_AXI_S_ARLOCK-1:0] w_arlock_s;
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wire [P_AXI_S_ARCACHE-1:0] w_arcache_s;
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wire [P_AXI_S_ARCACHE-1:0] w_arcache_s;
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wire [P_AXI_S_ARPROT-1:0] w_arprot_s;
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wire [P_AXI_S_ARPROT-1:0] w_arprot_s;
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wire [P_RC_FIFO_W-1:0] w_rc_fifo_in;
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wire [P_RC_FIFO_W-1:0] w_rc_fifo_in;
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wire [P_RC_FIFO_W-1:0] w_rc_fifo_out;
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wire [P_RC_FIFO_W-1:0] w_rc_fifo_out;
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wire w_rc_full;
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wire w_rc_full;
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wire w_rc_empty;
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wire w_rc_empty;
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wire w_rc_ren;
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wire w_rc_ren;
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// read response
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// read response
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wire [P_AXI_S_RID-1:0] w_rid_s;
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wire [P_AXI_S_RID-1:0] w_rid_s;
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wire [P_AXI_S_RDATA-1:0] w_rdata_s;
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wire [P_AXI_S_RDATA-1:0] w_rdata_s;
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wire [P_AXI_S_RRESP-1:0] w_rresp_s;
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wire [P_AXI_S_RRESP-1:0] w_rresp_s;
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wire w_rlast_s;
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wire w_rlast_s;
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wire [P_RR_FIFO_W-1:0] w_rr_fifo_in;
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wire [P_RR_FIFO_W-1:0] w_rr_fifo_in;
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wire [P_RR_FIFO_W-1:0] w_rr_fifo_out;
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wire [P_RR_FIFO_W-1:0] w_rr_fifo_out;
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wire w_rr_full;
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wire w_rr_full;
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wire w_rr_empty;
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wire w_rr_empty;
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wire w_rr_ren;
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wire w_rr_ren;
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//////////////////////////////////
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//////////////////////////////////
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// assign
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// assign
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//////////////////////////////////
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//////////////////////////////////
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assign o_awready_s = ~w_wc_full;
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assign o_awready_s = ~w_wc_full;
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assign w_wc_fifo_in = {
|
assign w_wc_fifo_in = {
|
i_awid_s,
|
i_awid_s,
|
i_awaddr_s,
|
i_awaddr_s,
|
i_awlen_s,
|
i_awlen_s,
|
i_awsize_s,
|
i_awsize_s,
|
i_awburst_s,
|
i_awburst_s,
|
i_awlock_s,
|
i_awlock_s,
|
i_awcache_s,
|
i_awcache_s,
|
i_awprot_s
|
i_awprot_s
|
};
|
};
|
|
|
assign {
|
assign {
|
w_awid_s,
|
w_awid_s,
|
w_awaddr_s,
|
w_awaddr_s,
|
w_awlen_s,
|
w_awlen_s,
|
w_awsize_s,
|
w_awsize_s,
|
w_awburst_s,
|
w_awburst_s,
|
w_awlock_s,
|
w_awlock_s,
|
w_awcache_s,
|
w_awcache_s,
|
w_awprot_s
|
w_awprot_s
|
} = w_wc_fifo_out;
|
} = w_wc_fifo_out;
|
|
|
assign o_wready_s = ~w_wd_full;
|
assign o_wready_s = ~w_wd_full;
|
assign w_wd_fifo_in = {
|
assign w_wd_fifo_in = {
|
i_wid_s,
|
i_wid_s,
|
i_wdata_s,
|
i_wdata_s,
|
i_wstrb_s,
|
i_wstrb_s,
|
i_wlast_s};
|
i_wlast_s};
|
|
|
assign {
|
assign {
|
w_wid_s,
|
w_wid_s,
|
w_wdata_s,
|
w_wdata_s,
|
w_wstrb_s,
|
w_wstrb_s,
|
w_wlast_s} = w_wd_fifo_out;
|
w_wlast_s} = w_wd_fifo_out;
|
|
|
assign w_bid_s = w_awid_s;
|
assign w_bid_s = w_awid_s;
|
assign w_bresp_s = {P_AXI_S_BRESP{1'b0}};
|
assign w_bresp_s = {P_AXI_S_BRESP{1'b0}};
|
assign w_wr_fifo_in = {
|
assign w_wr_fifo_in = {
|
w_bid_s,
|
w_bid_s,
|
w_bresp_s};
|
w_bresp_s};
|
|
|
assign {
|
assign {
|
o_bid_s,
|
o_bid_s,
|
o_bresp_s} = w_wr_fifo_out;
|
o_bresp_s} = w_wr_fifo_out;
|
|
|
assign o_bvalid_s = !w_wr_empty;
|
assign o_bvalid_s = !w_wr_empty;
|
assign w_rc_fifo_in = {
|
assign w_rc_fifo_in = {
|
i_arid_s,
|
i_arid_s,
|
i_araddr_s,
|
i_araddr_s,
|
i_arlen_s,
|
i_arlen_s,
|
i_arsize_s,
|
i_arsize_s,
|
i_arburst_s,
|
i_arburst_s,
|
i_arlock_s,
|
i_arlock_s,
|
i_arcache_s,
|
i_arcache_s,
|
i_arprot_s};
|
i_arprot_s};
|
|
|
assign o_arready_s = ~w_rc_full;
|
assign o_arready_s = ~w_rc_full;
|
assign {
|
assign {
|
w_arid_s,
|
w_arid_s,
|
w_araddr_s,
|
w_araddr_s,
|
w_arlen_s,
|
w_arlen_s,
|
w_arsize_s,
|
w_arsize_s,
|
w_arburst_s,
|
w_arburst_s,
|
w_arlock_s,
|
w_arlock_s,
|
w_arcache_s,
|
w_arcache_s,
|
w_arprot_s} = w_rc_fifo_out;
|
w_arprot_s} = w_rc_fifo_out;
|
|
|
assign {
|
assign {
|
o_rid_s,
|
o_rid_s,
|
o_rdata_s,
|
o_rdata_s,
|
o_rresp_s,
|
o_rresp_s,
|
o_rlast_s} = w_rr_fifo_out;
|
o_rlast_s} = w_rr_fifo_out;
|
|
|
assign w_rresp_s = {P_AXI_S_RRESP{1'b0}};
|
assign w_rresp_s = {P_AXI_S_RRESP{1'b0}};
|
assign w_rlast_s = 1'b1;
|
assign w_rlast_s = 1'b1;
|
assign w_rr_fifo_in = {
|
assign w_rr_fifo_in = {
|
r_arid_s,
|
r_arid_s,
|
i_rd,
|
i_rd,
|
w_rresp_s,
|
w_rresp_s,
|
w_rlast_s};
|
w_rlast_s};
|
|
|
assign o_rvalid_s = !w_rr_empty;
|
assign o_rvalid_s = !w_rr_empty;
|
assign w_w_access = !w_wc_empty & !w_wd_empty;
|
assign w_w_access = !w_wc_empty & !w_wd_empty;
|
assign w_r_access = !w_rc_empty;
|
assign w_r_access = !w_rc_empty;
|
assign w_wc_ren = (r_state == P_WRITE_CMD) & i_ack;
|
assign w_wc_ren = (r_state == P_WRITE_CMD) & i_ack;
|
assign w_wd_ren = (r_state == P_WRITE_CMD) & i_ack;
|
assign w_wd_ren = (r_state == P_WRITE_CMD) & i_ack;
|
assign w_rc_ren = (r_state == P_READ_CMD) & i_ack;
|
assign w_rc_ren = (r_state == P_READ_CMD) & i_ack;
|
assign o_req = (r_state == P_WRITE_CMD) | (r_state == P_READ_CMD);
|
assign o_req = (r_state == P_WRITE_CMD) | (r_state == P_READ_CMD);
|
assign o_wr = (r_state == P_WRITE_CMD);
|
assign o_wr = (r_state == P_WRITE_CMD);
|
assign o_adrs = (r_state == P_WRITE_CMD) ? w_awaddr_s[23:0] : w_araddr_s[23:0];
|
assign o_adrs = (r_state == P_WRITE_CMD) ? w_awaddr_s[23:0] : w_araddr_s[23:0];
|
assign o_be = w_wstrb_s;
|
assign o_be = w_wstrb_s;
|
assign o_wd = w_wdata_s;
|
assign o_wd = w_wdata_s;
|
//////////////////////////////////
|
//////////////////////////////////
|
// always
|
// always
|
//////////////////////////////////
|
//////////////////////////////////
|
always @(posedge clk_core) begin
|
always @(posedge clk_core) begin
|
if ((r_state == P_IDLE) & w_r_access) r_arid_s <= w_arid_s;
|
if ((r_state == P_IDLE) & w_r_access) r_arid_s <= w_arid_s;
|
end
|
end
|
|
|
always @(posedge clk_core or negedge rst_x) begin
|
always @(posedge clk_core or negedge rst_x) begin
|
if (~rst_x) begin
|
if (~rst_x) begin
|
r_state <= P_IDLE;
|
r_state <= P_IDLE;
|
end else begin
|
end else begin
|
case (r_state)
|
case (r_state)
|
P_IDLE : begin
|
P_IDLE : begin
|
if (w_w_access) r_state <= P_WRITE_CMD;
|
if (w_w_access) r_state <= P_WRITE_CMD;
|
else if (w_r_access) r_state <= P_READ_CMD;
|
else if (w_r_access) r_state <= P_READ_CMD;
|
end
|
end
|
P_WRITE_CMD : begin
|
P_WRITE_CMD : begin
|
if (i_ack) r_state <= P_IDLE;
|
if (i_ack) r_state <= P_IDLE;
|
end
|
end
|
P_READ_CMD : begin
|
P_READ_CMD : begin
|
if (i_ack) begin
|
if (i_ack) begin
|
if (i_rstr) r_state <= P_IDLE;
|
if (i_rstr) r_state <= P_IDLE;
|
else r_state <= P_READ_DT;
|
else r_state <= P_READ_DT;
|
end
|
end
|
end
|
end
|
P_READ_DT : begin
|
P_READ_DT : begin
|
if (i_rstr) r_state <= P_IDLE;
|
if (i_rstr) r_state <= P_IDLE;
|
end
|
end
|
|
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
|
|
//////////////////////////////////
|
//////////////////////////////////
|
// module instance
|
// module instance
|
//////////////////////////////////
|
//////////////////////////////////
|
// AXI write command
|
// AXI write command
|
fm_fifo #(P_WC_FIFO_W) u_wc_fifo (
|
fm_fifo #(P_WC_FIFO_W) u_wc_fifo (
|
.clk_core(clk_core),
|
.clk_core(clk_core),
|
.rst_x(rst_x),
|
.rst_x(rst_x),
|
.i_wstrobe(i_awvalid_s),
|
.i_wstrobe(i_awvalid_s),
|
.i_dt(w_wc_fifo_in),
|
.i_dt(w_wc_fifo_in),
|
.o_full(w_wc_full),
|
.o_full(w_wc_full),
|
.i_renable(w_wc_ren),
|
.i_renable(w_wc_ren),
|
.o_dt(w_wc_fifo_out),
|
.o_dt(w_wc_fifo_out),
|
.o_empty(w_wc_empty),
|
.o_empty(w_wc_empty),
|
.o_dnum()
|
.o_dnum()
|
);
|
);
|
// AXI write data
|
// AXI write data
|
fm_fifo #(P_WD_FIFO_W) u_wd_fifo (
|
fm_fifo #(P_WD_FIFO_W) u_wd_fifo (
|
.clk_core(clk_core),
|
.clk_core(clk_core),
|
.rst_x(rst_x),
|
.rst_x(rst_x),
|
.i_wstrobe(i_wvalid_s),
|
.i_wstrobe(i_wvalid_s),
|
.i_dt(w_wd_fifo_in),
|
.i_dt(w_wd_fifo_in),
|
.o_full(w_wd_full),
|
.o_full(w_wd_full),
|
.i_renable(w_wd_ren),
|
.i_renable(w_wd_ren),
|
.o_dt(w_wd_fifo_out),
|
.o_dt(w_wd_fifo_out),
|
.o_empty(w_wd_empty),
|
.o_empty(w_wd_empty),
|
.o_dnum()
|
.o_dnum()
|
);
|
);
|
// AXI write response
|
// AXI write response
|
fm_fifo #(P_WR_FIFO_W) u_wr_fifo (
|
fm_fifo #(P_WR_FIFO_W) u_wr_fifo (
|
.clk_core(clk_core),
|
.clk_core(clk_core),
|
.rst_x(rst_x),
|
.rst_x(rst_x),
|
.i_wstrobe(w_wd_ren),
|
.i_wstrobe(w_wd_ren),
|
.i_dt(w_wr_fifo_in),
|
.i_dt(w_wr_fifo_in),
|
.o_full(w_wr_full),
|
.o_full(w_wr_full),
|
.i_renable(i_bready_s),
|
.i_renable(i_bready_s),
|
.o_dt(w_wr_fifo_out),
|
.o_dt(w_wr_fifo_out),
|
.o_empty(w_wr_empty),
|
.o_empty(w_wr_empty),
|
.o_dnum()
|
.o_dnum()
|
);
|
);
|
// AXI read command
|
// AXI read command
|
fm_fifo #(P_RC_FIFO_W) u_rc_fifo (
|
fm_fifo #(P_RC_FIFO_W) u_rc_fifo (
|
.clk_core(clk_core),
|
.clk_core(clk_core),
|
.rst_x(rst_x),
|
.rst_x(rst_x),
|
.i_wstrobe(i_arvalid_s),
|
.i_wstrobe(i_arvalid_s),
|
.i_dt(w_rc_fifo_in),
|
.i_dt(w_rc_fifo_in),
|
.o_full(w_rc_full),
|
.o_full(w_rc_full),
|
.i_renable(w_rc_ren),
|
.i_renable(w_rc_ren),
|
.o_dt(w_rc_fifo_out),
|
.o_dt(w_rc_fifo_out),
|
.o_empty(w_rc_empty),
|
.o_empty(w_rc_empty),
|
.o_dnum()
|
.o_dnum()
|
);
|
);
|
// AXI read data
|
// AXI read data
|
fm_fifo #(P_RR_FIFO_W) u_rr_fifo (
|
fm_fifo #(P_RR_FIFO_W) u_rr_fifo (
|
.clk_core(clk_core),
|
.clk_core(clk_core),
|
.rst_x(rst_x),
|
.rst_x(rst_x),
|
.i_wstrobe(i_rstr),
|
.i_wstrobe(i_rstr),
|
.i_dt(w_rr_fifo_in),
|
.i_dt(w_rr_fifo_in),
|
.o_full(w_rr_full),
|
.o_full(w_rr_full),
|
.i_renable(i_rready_s),
|
.i_renable(i_rready_s),
|
.o_dt(w_rr_fifo_out),
|
.o_dt(w_rr_fifo_out),
|
.o_empty(w_rr_empty),
|
.o_empty(w_rr_empty),
|
.o_dnum()
|
.o_dnum()
|
);
|
);
|
|
|
endmodule
|
endmodule
|
|
|
|
|