//=======================================================================
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//=======================================================================
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// Project Monophony
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// Project Monophony
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// Wire-Frame 3D Graphics Accelerator IP Core
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// Wire-Frame 3D Graphics Accelerator IP Core
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//
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//
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// File:
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// File:
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// fm_cmn_bfifo.v
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// fm_cmn_bfifo.v
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//
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//
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// Abstract:
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// Abstract:
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// Block RAM FIFO
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// Block RAM FIFO
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//
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//
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// Author:
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// Author:
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// Kenji Ishimaru (info.wf3d@gmail.com)
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// Kenji Ishimaru (info.info.wf3d@gmail.com)
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//
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//
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//======================================================================
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//======================================================================
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//
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//
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// Copyright (c) 2016, Kenji Ishimaru
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// Copyright (c) 2016, Kenji Ishimaru
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// All rights reserved.
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// All rights reserved.
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// modification, are permitted provided that the following conditions are met:
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//
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//
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// -Redistributions of source code must retain the above copyright notice,
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// -Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// this list of conditions and the following disclaimer.
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// -Redistributions in binary form must reproduce the above copyright notice,
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// -Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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// and/or other materials provided with the distribution.
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//
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//
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// Revision History
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// Revision History
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module fm_cmn_bfifo (
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module fm_cmn_bfifo (
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clk_core,
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clk_core,
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rst_x,
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rst_x,
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i_wstrobe,
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i_wstrobe,
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i_dt,
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i_dt,
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o_full,
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o_full,
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i_renable,
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i_renable,
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o_dt,
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o_dt,
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o_empty,
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o_empty,
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o_dnum
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o_dnum
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);
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);
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// set default parameters
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// set default parameters
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parameter P_WIDTH = 32;
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parameter P_WIDTH = 32;
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parameter P_RANGE = 8;
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parameter P_RANGE = 8;
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parameter P_DEPTH = 1 << P_RANGE;
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parameter P_DEPTH = 1 << P_RANGE;
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////////////////////////////
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////////////////////////////
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// I/O definition
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// I/O definition
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////////////////////////////
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////////////////////////////
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input clk_core; // system clock
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input clk_core; // system clock
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input rst_x; // system reset
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input rst_x; // system reset
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input i_wstrobe; // write strobe
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input i_wstrobe; // write strobe
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input [P_WIDTH-1:0] i_dt; // write data
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input [P_WIDTH-1:0] i_dt; // write data
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output o_full; // write data full
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output o_full; // write data full
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input i_renable; // read enable
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input i_renable; // read enable
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output [P_WIDTH-1:0] o_dt; // read data
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output [P_WIDTH-1:0] o_dt; // read data
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output o_empty; // read data empty
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output o_empty; // read data empty
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output [P_RANGE:0] o_dnum; // written data number
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output [P_RANGE:0] o_dnum; // written data number
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/////////////////////////
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/////////////////////////
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// Register definition
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// Register definition
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/////////////////////////
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/////////////////////////
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reg [P_RANGE-1:0] r_write_counter;
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reg [P_RANGE-1:0] r_write_counter;
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reg [P_RANGE-1:0] r_read_counter;
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reg [P_RANGE-1:0] r_read_counter;
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reg [P_RANGE:0] r_status;
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reg [P_RANGE:0] r_status;
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reg r_sel;
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reg r_sel;
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/////////////////////////
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/////////////////////////
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// wire definition
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// wire definition
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/////////////////////////
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/////////////////////////
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wire o_full;
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wire o_full;
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wire [P_WIDTH-1:0] o_dt;
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wire [P_WIDTH-1:0] o_dt;
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wire [P_WIDTH-1:0] w_dto;
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wire [P_WIDTH-1:0] w_dto;
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wire [P_WIDTH-1:0] w_dto_th;
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wire [P_WIDTH-1:0] w_dto_th;
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wire [1:0] w_status;
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wire [1:0] w_status;
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wire w_we;
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wire w_we;
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wire w_re;
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wire w_re;
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wire [P_RANGE-1:0] w_read_counter_inc;
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wire [P_RANGE-1:0] w_read_counter_inc;
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wire [P_RANGE-1:0] w_read_counter;
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wire [P_RANGE-1:0] w_read_counter;
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/////////////////////////
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/////////////////////////
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// assign statement
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// assign statement
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/////////////////////////
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/////////////////////////
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assign o_full = (r_status == P_DEPTH);
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assign o_full = (r_status == P_DEPTH);
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assign o_empty = (r_status == 0);
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assign o_empty = (r_status == 0);
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assign o_dnum = r_status;
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assign o_dnum = r_status;
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assign o_dt = (r_sel) ? w_dto_th : w_dto;
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assign o_dt = (r_sel) ? w_dto_th : w_dto;
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assign w_read_counter_inc = r_read_counter + 1'b1;
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assign w_read_counter_inc = r_read_counter + 1'b1;
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assign w_read_counter = (w_re) ? w_read_counter_inc : r_read_counter;
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assign w_read_counter = (w_re) ? w_read_counter_inc : r_read_counter;
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assign w_we = !o_full & i_wstrobe;
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assign w_we = !o_full & i_wstrobe;
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assign w_re = i_renable & !o_empty;
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assign w_re = i_renable & !o_empty;
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assign w_status = {w_re,w_we};
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assign w_status = {w_re,w_we};
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////////////////////////
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////////////////////////
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// always statement
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// always statement
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///////////////////////
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///////////////////////
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// write side
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// write side
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always @(posedge clk_core or negedge rst_x) begin
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always @(posedge clk_core or negedge rst_x) begin
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if (~rst_x) begin
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if (~rst_x) begin
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r_write_counter <= 'd0;
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r_write_counter <= 'd0;
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end else begin
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end else begin
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if (w_we) begin
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if (w_we) begin
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r_write_counter <= r_write_counter + 1'b1;
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r_write_counter <= r_write_counter + 1'b1;
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end
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end
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end
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end
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end
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end
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// read side
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// read side
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always @(posedge clk_core or negedge rst_x) begin
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always @(posedge clk_core or negedge rst_x) begin
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if (~rst_x) begin
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if (~rst_x) begin
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r_read_counter <= 'd0;
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r_read_counter <= 'd0;
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end else begin
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end else begin
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if (w_re) begin
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if (w_re) begin
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r_read_counter <= w_read_counter_inc;
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r_read_counter <= w_read_counter_inc;
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end
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end
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end
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end
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end
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end
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// ram output select
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// ram output select
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always @(posedge clk_core or negedge rst_x) begin
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always @(posedge clk_core or negedge rst_x) begin
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if (~rst_x) begin
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if (~rst_x) begin
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r_sel <= 1'b0;
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r_sel <= 1'b0;
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end else begin
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end else begin
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r_sel <= (r_write_counter == w_read_counter) ? 1'b1 : 1'b0;
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r_sel <= (r_write_counter == w_read_counter) ? 1'b1 : 1'b0;
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end
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end
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end
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end
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// status counter
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// status counter
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always @(posedge clk_core or negedge rst_x) begin
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always @(posedge clk_core or negedge rst_x) begin
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if (~rst_x) begin
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if (~rst_x) begin
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r_status <= 'd0;
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r_status <= 'd0;
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end else begin
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end else begin
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case (w_status)
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case (w_status)
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2'b01: r_status <= r_status + 1'b1; // write
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2'b01: r_status <= r_status + 1'b1; // write
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2'b10: r_status <= r_status - 1'b1; // read
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2'b10: r_status <= r_status - 1'b1; // read
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default: r_status <= r_status; // nothing to do
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default: r_status <= r_status; // nothing to do
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endcase
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endcase
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end
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end
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end
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end
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///////////////////
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///////////////////
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// module instance
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// module instance
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///////////////////
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///////////////////
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fm_cmn_bram_01 #(P_WIDTH, P_RANGE) bram_00 (
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fm_cmn_bram_01 #(P_WIDTH, P_RANGE) bram_00 (
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.clk(clk_core),
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.clk(clk_core),
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.we(w_we),
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.we(w_we),
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.a(r_write_counter),
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.a(r_write_counter),
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.dpra(w_read_counter),
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.dpra(w_read_counter),
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.di(i_dt),
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.di(i_dt),
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.spo(w_dto_th),
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.spo(w_dto_th),
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.dpo(w_dto)
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.dpo(w_dto)
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);
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);
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endmodule
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endmodule
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