//=======================================================================
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//=======================================================================
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// Project Monophony
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// Project Monophony
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// Wire-Frame 3D Graphics Accelerator IP Core
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// Wire-Frame 3D Graphics Accelerator IP Core
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//
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//
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// File:
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// File:
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// fm_dma.v
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// fm_dma.v
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//
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//
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// Abstract:
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// Abstract:
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// DMA controller for buffer clear
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// DMA controller for buffer clear
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//
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//
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// Author:
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// Author:
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// Kenji Ishimaru (info.wf3d@gmail.com)
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// Kenji Ishimaru (info.info.wf3d@gmail.com)
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//
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//
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//======================================================================
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//======================================================================
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//
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//
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// Copyright (c) 2016, Kenji Ishimaru
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// Copyright (c) 2016, Kenji Ishimaru
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// All rights reserved.
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// All rights reserved.
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// modification, are permitted provided that the following conditions are met:
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//
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//
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// -Redistributions of source code must retain the above copyright notice,
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// -Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// this list of conditions and the following disclaimer.
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// -Redistributions in binary form must reproduce the above copyright notice,
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// -Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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// and/or other materials provided with the distribution.
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//
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//
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// Revision History
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// Revision History
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module fm_dma (
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module fm_dma (
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clk_core,
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clk_core,
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rst_x,
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rst_x,
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// DMA
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// DMA
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i_dma_start,
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i_dma_start,
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i_dma_mode,
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i_dma_mode,
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o_dma_end,
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o_dma_end,
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i_dma_top_address0,
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i_dma_top_address0,
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i_dma_top_address1,
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i_dma_top_address1,
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i_dma_top_address2,
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i_dma_top_address2,
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i_dma_top_address3,
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i_dma_top_address3,
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i_dma_length,
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i_dma_length,
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i_dma_be,
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i_dma_be,
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i_dma_wd0,
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i_dma_wd0,
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i_dma_wd1,
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i_dma_wd1,
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// memory access
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// memory access
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o_req_mem,
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o_req_mem,
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o_wr_mem,
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o_wr_mem,
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o_adrs_mem,
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o_adrs_mem,
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o_len_mem,
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o_len_mem,
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i_ack_mem,
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i_ack_mem,
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o_strw_mem,
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o_strw_mem,
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o_be_mem,
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o_be_mem,
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o_wd_mem,
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o_wd_mem,
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i_ackw_mem
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i_ackw_mem
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);
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);
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//////////////////////////////////
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//////////////////////////////////
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// I/O port definition
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// I/O port definition
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//////////////////////////////////
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//////////////////////////////////
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`include "polyphony_params.v"
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`include "polyphony_params.v"
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input clk_core;
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input clk_core;
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input rst_x;
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input rst_x;
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// DMA
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// DMA
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input i_dma_start;
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input i_dma_start;
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input [3:0] i_dma_mode;
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input [3:0] i_dma_mode;
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output o_dma_end;
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output o_dma_end;
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input [19:0] i_dma_top_address0;
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input [19:0] i_dma_top_address0;
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input [19:0] i_dma_top_address1;
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input [19:0] i_dma_top_address1;
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input [19:0] i_dma_top_address2;
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input [19:0] i_dma_top_address2;
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input [19:0] i_dma_top_address3;
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input [19:0] i_dma_top_address3;
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input [17:0] i_dma_length;
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input [17:0] i_dma_length;
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input [3:0] i_dma_be;
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input [3:0] i_dma_be;
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input [31:0] i_dma_wd0;
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input [31:0] i_dma_wd0;
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input [31:0] i_dma_wd1;
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input [31:0] i_dma_wd1;
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// sdram interface
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// sdram interface
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output o_req_mem;
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output o_req_mem;
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output o_wr_mem;
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output o_wr_mem;
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output [P_IB_ADDR_WIDTH-1:0] o_adrs_mem;
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output [P_IB_ADDR_WIDTH-1:0] o_adrs_mem;
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output [P_IB_LEN_WIDTH-1:0] o_len_mem;
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output [P_IB_LEN_WIDTH-1:0] o_len_mem;
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input i_ack_mem;
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input i_ack_mem;
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output o_strw_mem;
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output o_strw_mem;
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output [P_IB_BE_WIDTH-1:0] o_be_mem;
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output [P_IB_BE_WIDTH-1:0] o_be_mem;
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output [P_IB_DATA_WIDTH-1:0] o_wd_mem;
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output [P_IB_DATA_WIDTH-1:0] o_wd_mem;
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input i_ackw_mem;
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input i_ackw_mem;
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// dma
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// dma
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wire w_req_dma;
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wire w_req_dma;
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wire w_wr_dma;
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wire w_wr_dma;
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wire [P_IB_ADDR_WIDTH-1:0] w_adrs_dma;
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wire [P_IB_ADDR_WIDTH-1:0] w_adrs_dma;
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wire [P_IB_LEN_WIDTH-1:0] w_len_dma;
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wire [P_IB_LEN_WIDTH-1:0] w_len_dma;
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wire w_ack_dma;
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wire w_ack_dma;
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wire w_strw_dma;
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wire w_strw_dma;
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wire [P_IB_BE_WIDTH-1:0] w_be_dma;
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wire [P_IB_BE_WIDTH-1:0] w_be_dma;
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wire [P_IB_DATA_WIDTH-1:0] w_wd_dma;
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wire [P_IB_DATA_WIDTH-1:0] w_wd_dma;
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wire w_ackw_dma;
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wire w_ackw_dma;
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//////////////////////////////////
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//////////////////////////////////
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// assign
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// assign
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//////////////////////////////////
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//////////////////////////////////
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//////////////////////////////////
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//////////////////////////////////
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// module instance
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// module instance
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//////////////////////////////////
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//////////////////////////////////
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fm_dispatch_dma dispatch_dma (
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fm_dispatch_dma dispatch_dma (
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.clk_core(clk_core),
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.clk_core(clk_core),
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.rst_x(rst_x),
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.rst_x(rst_x),
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// system port
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// system port
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.i_dma_start(i_dma_start),
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.i_dma_start(i_dma_start),
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.i_dma_mode(i_dma_mode),
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.i_dma_mode(i_dma_mode),
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.o_dma_end(o_dma_end),
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.o_dma_end(o_dma_end),
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.i_dma_top_address0(i_dma_top_address0),
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.i_dma_top_address0(i_dma_top_address0),
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.i_dma_top_address1(i_dma_top_address1),
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.i_dma_top_address1(i_dma_top_address1),
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.i_dma_top_address2(i_dma_top_address2),
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.i_dma_top_address2(i_dma_top_address2),
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.i_dma_top_address3(i_dma_top_address3),
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.i_dma_top_address3(i_dma_top_address3),
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.i_dma_length(i_dma_length),
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.i_dma_length(i_dma_length),
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.i_dma_be(i_dma_be),
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.i_dma_be(i_dma_be),
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.i_dma_wd0(i_dma_wd0),
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.i_dma_wd0(i_dma_wd0),
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.i_dma_wd1(i_dma_wd1),
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.i_dma_wd1(i_dma_wd1),
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// memory port
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// memory port
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.o_req(w_req_dma),
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.o_req(w_req_dma),
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.o_wr(w_wr_dma),
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.o_wr(w_wr_dma),
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.o_adrs(w_adrs_dma),
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.o_adrs(w_adrs_dma),
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.o_len(w_len_dma),
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.o_len(w_len_dma),
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.i_ack(w_ack_dma),
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.i_ack(w_ack_dma),
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.o_strw(w_strw_dma),
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.o_strw(w_strw_dma),
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.o_be(w_be_dma),
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.o_be(w_be_dma),
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.o_wd(w_wd_dma),
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.o_wd(w_wd_dma),
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.i_ackw(w_ackw_dma)
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.i_ackw(w_ackw_dma)
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);
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);
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fm_cmn_if_ff_out #(P_IB_ADDR_WIDTH,
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fm_cmn_if_ff_out #(P_IB_ADDR_WIDTH,
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P_IB_DATA_WIDTH,
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P_IB_DATA_WIDTH,
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P_IB_LEN_WIDTH) if_ff_out (
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P_IB_LEN_WIDTH) if_ff_out (
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.clk_core(clk_core),
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.clk_core(clk_core),
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.rst_x(rst_x),
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.rst_x(rst_x),
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// local interface
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// local interface
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.i_req(w_req_dma),
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.i_req(w_req_dma),
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.i_wr(w_wr_dma),
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.i_wr(w_wr_dma),
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.i_adrs(w_adrs_dma),
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.i_adrs(w_adrs_dma),
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.i_len(w_len_dma),
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.i_len(w_len_dma),
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.o_ack(w_ack_dma),
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.o_ack(w_ack_dma),
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.i_strw(w_strw_dma),
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.i_strw(w_strw_dma),
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.i_be(w_be_dma),
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.i_be(w_be_dma),
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.i_dbw(w_wd_dma),
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.i_dbw(w_wd_dma),
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.o_ackw(w_ackw_dma),
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.o_ackw(w_ackw_dma),
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.o_strr(),
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.o_strr(),
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.o_dbr(),
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.o_dbr(),
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// F/F interface
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// F/F interface
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.o_req(o_req_mem),
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.o_req(o_req_mem),
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.o_wr(o_wr_mem),
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.o_wr(o_wr_mem),
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.o_adrs(o_adrs_mem),
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.o_adrs(o_adrs_mem),
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.o_len(o_len_mem),
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.o_len(o_len_mem),
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.i_ack(i_ack_mem),
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.i_ack(i_ack_mem),
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.o_strw(o_strw_mem),
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.o_strw(o_strw_mem),
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.o_be(o_be_mem),
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.o_be(o_be_mem),
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.o_dbw(o_wd_mem),
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.o_dbw(o_wd_mem),
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.i_ackw(i_ackw_mem),
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.i_ackw(i_ackw_mem),
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.i_strr(1'b0),
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.i_strr(1'b0),
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.i_dbr({P_IB_DATA_WIDTH{1'b0}})
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.i_dbr({P_IB_DATA_WIDTH{1'b0}})
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);
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);
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endmodule
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endmodule
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