//=======================================================================
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//=======================================================================
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// Project Monophony
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// Project Monophony
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// Wire-Frame 3D Graphics Accelerator IP Core
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// Wire-Frame 3D Graphics Accelerator IP Core
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//
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//
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// File:
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// File:
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// fm_mic.v
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// fm_mic.v
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//
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//
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// Abstract:
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// Abstract:
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// Memory Interconnect top module
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// Memory Interconnect top module
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//
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//
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// Author:
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// Author:
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// Kenji Ishimaru (info.wf3d@gmail.com)
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// Kenji Ishimaru (info.info.wf3d@gmail.com)
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//
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//
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//======================================================================
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//======================================================================
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//
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//
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// Copyright (c) 2015, Kenji Ishimaru
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// Copyright (c) 2015, Kenji Ishimaru
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// All rights reserved.
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// All rights reserved.
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// modification, are permitted provided that the following conditions are met:
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//
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//
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// -Redistributions of source code must retain the above copyright notice,
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// -Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// this list of conditions and the following disclaimer.
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// -Redistributions in binary form must reproduce the above copyright notice,
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// -Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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// and/or other materials provided with the distribution.
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//
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//
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// Revision History
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// Revision History
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module fm_mic (
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module fm_mic (
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clk_core,
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clk_core,
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rst_x,
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rst_x,
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// write/read port 0 (vertex fetch)
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// write/read port 0 (vertex fetch)
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i_wr_req0,
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i_wr_req0,
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i_wr_wr0,
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i_wr_wr0,
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i_wr_adrs0,
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i_wr_adrs0,
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i_wr_len0,
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i_wr_len0,
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o_wr_ack0,
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o_wr_ack0,
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i_wr_wstr0,
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i_wr_wstr0,
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i_wr_be0,
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i_wr_be0,
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i_wr_wdata0,
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i_wr_wdata0,
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o_wr_wack0,
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o_wr_wack0,
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o_wr_rstr0,
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o_wr_rstr0,
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o_wr_rdata0,
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o_wr_rdata0,
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// read/write port 1 (3D read/write)
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// read/write port 1 (3D read/write)
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i_wr_req1,
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i_wr_req1,
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i_wr_wr1,
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i_wr_wr1,
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i_wr_adrs1,
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i_wr_adrs1,
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i_wr_len1,
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i_wr_len1,
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o_wr_ack1,
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o_wr_ack1,
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i_wr_be1,
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i_wr_be1,
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i_wr_wdata1,
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i_wr_wdata1,
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o_wr_rstr1,
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o_wr_rstr1,
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o_wr_rdata1,
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o_wr_rdata1,
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// read port 2 (ctr controller)
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// read port 2 (ctr controller)
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i_r_req2,
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i_r_req2,
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i_r_adrs2,
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i_r_adrs2,
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i_r_len2,
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i_r_len2,
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o_r_ack2,
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o_r_ack2,
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o_r_rstr2,
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o_r_rstr2,
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o_r_rdata2,
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o_r_rdata2,
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// write port 3 (DMA write)
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// write port 3 (DMA write)
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i_wr_req3,
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i_wr_req3,
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i_wr_adrs3,
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i_wr_adrs3,
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i_wr_len3,
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i_wr_len3,
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o_wr_ack3,
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o_wr_ack3,
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i_wr_wstr3,
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i_wr_wstr3,
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i_wr_be3,
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i_wr_be3,
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i_wr_wdata3,
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i_wr_wdata3,
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o_wr_wack3,
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o_wr_wack3,
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// DIMM Bridge Interface
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// DIMM Bridge Interface
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o_brg_req,
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o_brg_req,
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o_brg_wr,
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o_brg_wr,
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o_brg_id,
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o_brg_id,
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o_brg_adrs,
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o_brg_adrs,
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o_brg_len,
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o_brg_len,
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i_brg_ack,
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i_brg_ack,
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o_brg_wstr,
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o_brg_wstr,
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o_brg_be,
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o_brg_be,
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o_brg_wdata,
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o_brg_wdata,
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i_brg_wack,
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i_brg_wack,
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i_brg_rstr,
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i_brg_rstr,
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i_brg_rlast,
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i_brg_rlast,
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i_brg_rid,
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i_brg_rid,
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i_brg_rdata
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i_brg_rdata
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);
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);
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`include "polyphony_params.v"
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`include "polyphony_params.v"
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//////////////////////////////////
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//////////////////////////////////
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// I/O port definition
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// I/O port definition
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//////////////////////////////////
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//////////////////////////////////
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input clk_core;
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input clk_core;
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input rst_x;
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input rst_x;
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// write/read port 0
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// write/read port 0
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input i_wr_req0;
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input i_wr_req0;
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input i_wr_wr0;
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input i_wr_wr0;
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input [P_IB_ADDR_WIDTH-1:0] i_wr_adrs0;
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input [P_IB_ADDR_WIDTH-1:0] i_wr_adrs0;
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input [P_IB_LEN_WIDTH-1:0] i_wr_len0;
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input [P_IB_LEN_WIDTH-1:0] i_wr_len0;
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output o_wr_ack0;
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output o_wr_ack0;
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input i_wr_wstr0;
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input i_wr_wstr0;
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input [P_IB_BE_WIDTH-1:0] i_wr_be0;
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input [P_IB_BE_WIDTH-1:0] i_wr_be0;
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input [P_IB_DATA_WIDTH-1:0] i_wr_wdata0;
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input [P_IB_DATA_WIDTH-1:0] i_wr_wdata0;
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output o_wr_wack0;
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output o_wr_wack0;
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output o_wr_rstr0;
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output o_wr_rstr0;
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output [P_IB_DATA_WIDTH-1:0] o_wr_rdata0;
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output [P_IB_DATA_WIDTH-1:0] o_wr_rdata0;
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// write/read port 1
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// write/read port 1
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input i_wr_req1;
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input i_wr_req1;
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input i_wr_wr1;
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input i_wr_wr1;
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input [31:0] i_wr_adrs1;
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input [31:0] i_wr_adrs1;
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input [2:0] i_wr_len1;
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input [2:0] i_wr_len1;
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output o_wr_ack1;
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output o_wr_ack1;
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input [3:0] i_wr_be1;
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input [3:0] i_wr_be1;
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input [31:0] i_wr_wdata1;
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input [31:0] i_wr_wdata1;
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output o_wr_rstr1;
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output o_wr_rstr1;
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output [31:0] o_wr_rdata1;
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output [31:0] o_wr_rdata1;
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// read port 2
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// read port 2
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input i_r_req2;
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input i_r_req2;
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input [P_IB_ADDR_WIDTH-1:0] i_r_adrs2;
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input [P_IB_ADDR_WIDTH-1:0] i_r_adrs2;
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input [P_IB_LEN_WIDTH-1:0] i_r_len2;
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input [P_IB_LEN_WIDTH-1:0] i_r_len2;
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output o_r_ack2;
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output o_r_ack2;
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output o_r_rstr2;
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output o_r_rstr2;
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output [P_IB_DATA_WIDTH-1:0] o_r_rdata2;
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output [P_IB_DATA_WIDTH-1:0] o_r_rdata2;
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// write port 3
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// write port 3
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input i_wr_req3;
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input i_wr_req3;
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input [P_IB_ADDR_WIDTH-1:0] i_wr_adrs3;
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input [P_IB_ADDR_WIDTH-1:0] i_wr_adrs3;
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input [P_IB_LEN_WIDTH-1:0] i_wr_len3;
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input [P_IB_LEN_WIDTH-1:0] i_wr_len3;
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output o_wr_ack3;
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output o_wr_ack3;
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input i_wr_wstr3;
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input i_wr_wstr3;
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input [P_IB_BE_WIDTH-1:0] i_wr_be3;
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input [P_IB_BE_WIDTH-1:0] i_wr_be3;
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input [P_IB_DATA_WIDTH-1:0] i_wr_wdata3;
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input [P_IB_DATA_WIDTH-1:0] i_wr_wdata3;
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output o_wr_wack3;
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output o_wr_wack3;
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// DIMM Bridge Interface
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// DIMM Bridge Interface
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output o_brg_req;
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output o_brg_req;
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output o_brg_wr;
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output o_brg_wr;
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output [1:0] o_brg_id;
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output [1:0] o_brg_id;
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(* mark_debug = "true" *)output [P_IB_ADDR_WIDTH-1:0] o_brg_adrs;
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(* mark_debug = "true" *)output [P_IB_ADDR_WIDTH-1:0] o_brg_adrs;
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output [P_IB_LEN_WIDTH-1:0] o_brg_len;
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output [P_IB_LEN_WIDTH-1:0] o_brg_len;
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input i_brg_ack;
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input i_brg_ack;
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output o_brg_wstr;
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output o_brg_wstr;
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output [P_IB_BE_WIDTH-1:0] o_brg_be;
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output [P_IB_BE_WIDTH-1:0] o_brg_be;
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output [P_IB_DATA_WIDTH-1:0] o_brg_wdata;
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output [P_IB_DATA_WIDTH-1:0] o_brg_wdata;
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input i_brg_wack;
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input i_brg_wack;
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input i_brg_rstr;
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input i_brg_rstr;
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input i_brg_rlast;
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input i_brg_rlast;
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input [1:0] i_brg_rid;
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input [1:0] i_brg_rid;
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input [P_IB_DATA_WIDTH-1:0] i_brg_rdata;
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input [P_IB_DATA_WIDTH-1:0] i_brg_rdata;
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//////////////////////////////////
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//////////////////////////////////
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// regs
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// regs
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//////////////////////////////////
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//////////////////////////////////
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//////////////////////////////////
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//////////////////////////////////
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// wires
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// wires
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//////////////////////////////////
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//////////////////////////////////
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// port0 command/data fifo (write/read)
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// port0 command/data fifo (write/read)
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wire [P_IB_ADDR_WIDTH+P_IB_LEN_WIDTH+1-1:0]
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wire [P_IB_ADDR_WIDTH+P_IB_LEN_WIDTH+1-1:0]
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w_fifo_cin0;
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w_fifo_cin0;
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wire [P_IB_DATA_WIDTH+P_IB_BE_WIDTH-1:0]
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wire [P_IB_DATA_WIDTH+P_IB_BE_WIDTH-1:0]
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w_fifo_din0; // write data bus + be
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w_fifo_din0; // write data bus + be
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wire [P_IB_ADDR_WIDTH+P_IB_LEN_WIDTH+1-1:0]
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wire [P_IB_ADDR_WIDTH+P_IB_LEN_WIDTH+1-1:0]
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w_fifo_cout0;
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w_fifo_cout0;
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wire [P_IB_DATA_WIDTH+P_IB_BE_WIDTH-1:0]
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wire [P_IB_DATA_WIDTH+P_IB_BE_WIDTH-1:0]
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w_fifo_dout0;
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w_fifo_dout0;
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wire w_cfifo_ack0;
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wire w_cfifo_ack0;
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wire w_dfifo_ack0;
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wire w_dfifo_ack0;
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// port3 command/data fifo
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// port3 command/data fifo
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wire [P_IB_ADDR_WIDTH+P_IB_LEN_WIDTH-1:0]
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wire [P_IB_ADDR_WIDTH+P_IB_LEN_WIDTH-1:0]
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w_fifo_cin3;
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w_fifo_cin3;
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wire [P_IB_DATA_WIDTH+P_IB_BE_WIDTH-1:0]
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wire [P_IB_DATA_WIDTH+P_IB_BE_WIDTH-1:0]
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w_fifo_din3; // write data bus + be
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w_fifo_din3; // write data bus + be
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wire [P_IB_ADDR_WIDTH+P_IB_LEN_WIDTH-1:0]
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wire [P_IB_ADDR_WIDTH+P_IB_LEN_WIDTH-1:0]
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w_fifo_cout3;
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w_fifo_cout3;
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wire [P_IB_DATA_WIDTH+P_IB_BE_WIDTH-1:0]
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wire [P_IB_DATA_WIDTH+P_IB_BE_WIDTH-1:0]
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w_fifo_dout3;
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w_fifo_dout3;
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wire w_cfifo_ack3;
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wire w_cfifo_ack3;
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wire w_dfifo_ack3;
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wire w_dfifo_ack3;
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// port 0
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// port 0
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wire w_req0;
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wire w_req0;
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wire w_we0;
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wire w_we0;
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wire [P_IB_ADDR_WIDTH-1:0] w_add0;
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wire [P_IB_ADDR_WIDTH-1:0] w_add0;
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wire [P_IB_LEN_WIDTH-1:0] w_len0;
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wire [P_IB_LEN_WIDTH-1:0] w_len0;
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wire [P_IB_BE_WIDTH-1:0] w_be0;
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wire [P_IB_BE_WIDTH-1:0] w_be0;
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wire w_cack0;
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wire w_cack0;
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wire w_strw0;
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wire w_strw0;
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wire [P_IB_DATA_WIDTH-1:0] w_dbw0;
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wire [P_IB_DATA_WIDTH-1:0] w_dbw0;
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wire w_wdata_read_end0;
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wire w_wdata_read_end0;
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wire w_wdata_ack0;
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wire w_wdata_ack0;
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wire w_strr0;
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wire w_strr0;
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wire [P_IB_DATA_WIDTH-1:0] w_dbr0;
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wire [P_IB_DATA_WIDTH-1:0] w_dbr0;
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// port 1
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// port 1
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wire w_req1;
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wire w_req1;
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wire w_we1;
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wire w_we1;
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wire [P_IB_ADDR_WIDTH-1:0] w_add1;
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wire [P_IB_ADDR_WIDTH-1:0] w_add1;
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wire w_ack1;
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wire w_ack1;
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wire w_cack1;
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wire w_cack1;
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wire [P_IB_LEN_WIDTH-1:0] w_len1;
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wire [P_IB_LEN_WIDTH-1:0] w_len1;
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wire [P_IB_BE_WIDTH-1:0] w_be1;
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wire [P_IB_BE_WIDTH-1:0] w_be1;
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wire [P_IB_DATA_WIDTH-1:0] w_dbw1;
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wire [P_IB_DATA_WIDTH-1:0] w_dbw1;
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wire w_rstr1;
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wire w_rstr1;
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wire [P_IB_DATA_WIDTH-1:0] w_rdata1;
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wire [P_IB_DATA_WIDTH-1:0] w_rdata1;
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// port 2
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// port 2
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wire w_cack2;
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wire w_cack2;
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// port 3
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// port 3
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wire w_req3;
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wire w_req3;
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wire [P_IB_ADDR_WIDTH-1:0] w_add3;
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wire [P_IB_ADDR_WIDTH-1:0] w_add3;
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wire [P_IB_LEN_WIDTH-1:0] w_len3;
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wire [P_IB_LEN_WIDTH-1:0] w_len3;
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wire [P_IB_BE_WIDTH-1:0] w_be3;
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wire [P_IB_BE_WIDTH-1:0] w_be3;
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wire w_cack3;
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wire w_cack3;
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wire w_strw3;
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wire w_strw3;
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wire [P_IB_DATA_WIDTH-1:0] w_dbw3;
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wire [P_IB_DATA_WIDTH-1:0] w_dbw3;
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wire w_wdata_read_end3;
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wire w_wdata_read_end3;
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wire w_wdata_ack3;
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wire w_wdata_ack3;
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//////////////////////////////////
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//////////////////////////////////
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// assign statement
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// assign statement
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//////////////////////////////////
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//////////////////////////////////
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// port0 (r/w)
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// port0 (r/w)
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assign w_fifo_cin0 = {i_wr_wr0,i_wr_adrs0,i_wr_len0};
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assign w_fifo_cin0 = {i_wr_wr0,i_wr_adrs0,i_wr_len0};
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assign w_fifo_din0 = {i_wr_be0,i_wr_wdata0};
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assign w_fifo_din0 = {i_wr_be0,i_wr_wdata0};
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assign {w_we0,w_add0,w_len0} = w_fifo_cout0;
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assign {w_we0,w_add0,w_len0} = w_fifo_cout0;
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assign {w_be0,w_dbw0} = w_fifo_dout0;
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assign {w_be0,w_dbw0} = w_fifo_dout0;
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// port3 (w)
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// port3 (w)
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assign w_fifo_cin3 = {i_wr_adrs3,i_wr_len3};
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assign w_fifo_cin3 = {i_wr_adrs3,i_wr_len3};
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assign w_fifo_din3 = {i_wr_be3,i_wr_wdata3};
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assign w_fifo_din3 = {i_wr_be3,i_wr_wdata3};
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assign {w_add3,w_len3} = w_fifo_cout3;
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assign {w_add3,w_len3} = w_fifo_cout3;
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assign {w_be3,w_dbw3} = w_fifo_dout3;
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assign {w_be3,w_dbw3} = w_fifo_dout3;
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//////////////////////////////////
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//////////////////////////////////
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// module instantiation
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// module instantiation
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//////////////////////////////////
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//////////////////////////////////
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// port0
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// port0
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// command interface
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// command interface
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fm_cinterface #(P_IB_ADDR_WIDTH+P_IB_LEN_WIDTH+1) u_cinterface0 (
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fm_cinterface #(P_IB_ADDR_WIDTH+P_IB_LEN_WIDTH+1) u_cinterface0 (
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.clk_core(clk_core),
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.clk_core(clk_core),
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.rst_x(rst_x),
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.rst_x(rst_x),
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// bus side port
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// bus side port
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.i_bstr(i_wr_req0),
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.i_bstr(i_wr_req0),
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.i_bdata(w_fifo_cin0),
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.i_bdata(w_fifo_cin0),
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.o_back(o_wr_ack0),
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.o_back(o_wr_ack0),
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// internal port
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// internal port
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.o_istr(w_req0),
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.o_istr(w_req0),
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.o_idata(w_fifo_cout0),
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.o_idata(w_fifo_cout0),
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.i_iack(w_cfifo_ack0)
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.i_iack(w_cfifo_ack0)
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);
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);
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// port0
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// port0
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// wtite data interface
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// wtite data interface
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fm_dinterface #(P_IB_BE_WIDTH+P_IB_DATA_WIDTH) u_dinterface0 (
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fm_dinterface #(P_IB_BE_WIDTH+P_IB_DATA_WIDTH) u_dinterface0 (
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.clk_core(clk_core),
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.clk_core(clk_core),
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.rst_x(rst_x),
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.rst_x(rst_x),
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// bus side port
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// bus side port
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.i_bstr(i_wr_wstr0),
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.i_bstr(i_wr_wstr0),
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.i_bdata(w_fifo_din0),
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.i_bdata(w_fifo_din0),
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.o_back(o_wr_wack0),
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.o_back(o_wr_wack0),
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// internal port
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// internal port
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.o_istr(w_strw0),
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.o_istr(w_strw0),
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.o_idata(w_fifo_dout0),
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.o_idata(w_fifo_dout0),
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.i_iack(w_dfifo_ack0)
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.i_iack(w_dfifo_ack0)
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);
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);
|
|
|
// port0
|
// port0
|
// controller
|
// controller
|
fm_port_unit u_port_unit0 (
|
fm_port_unit u_port_unit0 (
|
.clk_core(clk_core),
|
.clk_core(clk_core),
|
.rst_x(rst_x),
|
.rst_x(rst_x),
|
// port side
|
// port side
|
.i_req(w_req0),
|
.i_req(w_req0),
|
.i_we(w_we0),
|
.i_we(w_we0),
|
.i_len(w_len0),
|
.i_len(w_len0),
|
.o_ack(w_cfifo_ack0),
|
.o_ack(w_cfifo_ack0),
|
.i_strw(w_strw0),
|
.i_strw(w_strw0),
|
.o_ackw(w_dfifo_ack0),
|
.o_ackw(w_dfifo_ack0),
|
.o_strr(o_wr_rstr0),
|
.o_strr(o_wr_rstr0),
|
.o_dbr(o_wr_rdata0),
|
.o_dbr(o_wr_rdata0),
|
// internal
|
// internal
|
.i_cack(w_cack0),
|
.i_cack(w_cack0),
|
.o_wdata_read_end(w_wdata_read_end0),
|
.o_wdata_read_end(w_wdata_read_end0),
|
.i_wdata_ack(w_wdata_ack0),
|
.i_wdata_ack(w_wdata_ack0),
|
.i_strr(w_strr0),
|
.i_strr(w_strr0),
|
.i_dbr(w_dbr0)
|
.i_dbr(w_dbr0)
|
);
|
);
|
|
|
fm_mic_cnv u_mic_cnv (
|
fm_mic_cnv u_mic_cnv (
|
.clk_core(clk_core),
|
.clk_core(clk_core),
|
.rst_x(rst_x),
|
.rst_x(rst_x),
|
// incoming
|
// incoming
|
.i_req_in(i_wr_req1),
|
.i_req_in(i_wr_req1),
|
.i_wr_in(i_wr_wr1),
|
.i_wr_in(i_wr_wr1),
|
.i_adrs_in(i_wr_adrs1[31:2]),
|
.i_adrs_in(i_wr_adrs1[31:2]),
|
.i_len_in(i_wr_len1),
|
.i_len_in(i_wr_len1),
|
.o_ack_in(w_cack1),
|
.o_ack_in(w_cack1),
|
.i_be_in(i_wr_be1),
|
.i_be_in(i_wr_be1),
|
.i_wdata_in(i_wr_wdata1),
|
.i_wdata_in(i_wr_wdata1),
|
.o_rstr_in(o_wr_rstr1),
|
.o_rstr_in(o_wr_rstr1),
|
.o_rdata_in(o_wr_rdata1),
|
.o_rdata_in(o_wr_rdata1),
|
// outcoming
|
// outcoming
|
.o_req_out(w_req1),
|
.o_req_out(w_req1),
|
.o_wr_out(w_we1),
|
.o_wr_out(w_we1),
|
.o_adrs_out(w_add1),
|
.o_adrs_out(w_add1),
|
.o_len_out(w_len1),
|
.o_len_out(w_len1),
|
.i_ack_out(w_ack1),
|
.i_ack_out(w_ack1),
|
.o_be_out(w_be1),
|
.o_be_out(w_be1),
|
.o_wdata_out(w_dbw1),
|
.o_wdata_out(w_dbw1),
|
.i_rstr_out(w_rstr1),
|
.i_rstr_out(w_rstr1),
|
.i_rdata_out(w_rdata1)
|
.i_rdata_out(w_rdata1)
|
);
|
);
|
assign o_wr_ack1 = (i_wr_req1) ? w_cack1 : 1'b1;
|
assign o_wr_ack1 = (i_wr_req1) ? w_cack1 : 1'b1;
|
// port2
|
// port2
|
assign o_r_ack2 = (i_r_req2) ? w_cack2 : 1'b1;
|
assign o_r_ack2 = (i_r_req2) ? w_cack2 : 1'b1;
|
|
|
// port3
|
// port3
|
// command interface
|
// command interface
|
fm_cinterface #(P_IB_ADDR_WIDTH+P_IB_LEN_WIDTH) u_cinterface3 (
|
fm_cinterface #(P_IB_ADDR_WIDTH+P_IB_LEN_WIDTH) u_cinterface3 (
|
.clk_core(clk_core),
|
.clk_core(clk_core),
|
.rst_x(rst_x),
|
.rst_x(rst_x),
|
// bus side port
|
// bus side port
|
.i_bstr(i_wr_req3),
|
.i_bstr(i_wr_req3),
|
.i_bdata(w_fifo_cin3),
|
.i_bdata(w_fifo_cin3),
|
.o_back(o_wr_ack3),
|
.o_back(o_wr_ack3),
|
// internal port
|
// internal port
|
.o_istr(w_req3),
|
.o_istr(w_req3),
|
.o_idata(w_fifo_cout3),
|
.o_idata(w_fifo_cout3),
|
.i_iack(w_cfifo_ack3)
|
.i_iack(w_cfifo_ack3)
|
);
|
);
|
|
|
// port3
|
// port3
|
// wtite data interface
|
// wtite data interface
|
fm_dinterface #(P_IB_BE_WIDTH+P_IB_DATA_WIDTH) u_dinterface3 (
|
fm_dinterface #(P_IB_BE_WIDTH+P_IB_DATA_WIDTH) u_dinterface3 (
|
.clk_core(clk_core),
|
.clk_core(clk_core),
|
.rst_x(rst_x),
|
.rst_x(rst_x),
|
// bus side port
|
// bus side port
|
.i_bstr(i_wr_wstr3),
|
.i_bstr(i_wr_wstr3),
|
.i_bdata(w_fifo_din3),
|
.i_bdata(w_fifo_din3),
|
.o_back(o_wr_wack3),
|
.o_back(o_wr_wack3),
|
// internal port
|
// internal port
|
.o_istr(w_strw3),
|
.o_istr(w_strw3),
|
.o_idata(w_fifo_dout3),
|
.o_idata(w_fifo_dout3),
|
.i_iack(w_dfifo_ack3)
|
.i_iack(w_dfifo_ack3)
|
);
|
);
|
|
|
// port3
|
// port3
|
// controller
|
// controller
|
fm_port_unit u_port_unit3 (
|
fm_port_unit u_port_unit3 (
|
.clk_core(clk_core),
|
.clk_core(clk_core),
|
.rst_x(rst_x),
|
.rst_x(rst_x),
|
// port side
|
// port side
|
.i_req(w_req3),
|
.i_req(w_req3),
|
.i_we(1'b1),
|
.i_we(1'b1),
|
.i_len(w_len3),
|
.i_len(w_len3),
|
.o_ack(w_cfifo_ack3),
|
.o_ack(w_cfifo_ack3),
|
.i_strw(w_strw3),
|
.i_strw(w_strw3),
|
.o_ackw(w_dfifo_ack3),
|
.o_ackw(w_dfifo_ack3),
|
.o_strr(),
|
.o_strr(),
|
.o_dbr(),
|
.o_dbr(),
|
// internal
|
// internal
|
.i_cack(w_cack3),
|
.i_cack(w_cack3),
|
.o_wdata_read_end(w_wdata_read_end3),
|
.o_wdata_read_end(w_wdata_read_end3),
|
.i_wdata_ack(w_wdata_ack3),
|
.i_wdata_ack(w_wdata_ack3),
|
.i_strr(1'b0),
|
.i_strr(1'b0),
|
.i_dbr(64'h0)
|
.i_dbr(64'h0)
|
);
|
);
|
|
|
fm_port_priority u_port_priority (
|
fm_port_priority u_port_priority (
|
.clk_core(clk_core),
|
.clk_core(clk_core),
|
.rst_x(rst_x),
|
.rst_x(rst_x),
|
// port0 side Read/Write
|
// port0 side Read/Write
|
.i_req0(w_req0),
|
.i_req0(w_req0),
|
.i_we0(w_we0),
|
.i_we0(w_we0),
|
.i_add0(w_add0),
|
.i_add0(w_add0),
|
.i_len0(w_len0),
|
.i_len0(w_len0),
|
.i_be0(w_be0),
|
.i_be0(w_be0),
|
.o_cack0(w_cack0),
|
.o_cack0(w_cack0),
|
.i_strw0(w_strw0),
|
.i_strw0(w_strw0),
|
.i_dbw0(w_dbw0),
|
.i_dbw0(w_dbw0),
|
.i_wdata_read_end0(w_wdata_read_end0),
|
.i_wdata_read_end0(w_wdata_read_end0),
|
.o_wdata_ack0(w_wdata_ack0),
|
.o_wdata_ack0(w_wdata_ack0),
|
.o_strr0(w_strr0),
|
.o_strr0(w_strr0),
|
.o_dbr0(w_dbr0),
|
.o_dbr0(w_dbr0),
|
// port1 side Read/Write
|
// port1 side Read/Write
|
.i_req1(w_req1),
|
.i_req1(w_req1),
|
.i_we1(w_we1),
|
.i_we1(w_we1),
|
.i_add1(w_add1),
|
.i_add1(w_add1),
|
.i_len1(w_len1),
|
.i_len1(w_len1),
|
.i_be1(w_be1),
|
.i_be1(w_be1),
|
.o_cack1(w_ack1),
|
.o_cack1(w_ack1),
|
.i_strw1(w_req1),
|
.i_strw1(w_req1),
|
.i_dbw1(w_dbw1),
|
.i_dbw1(w_dbw1),
|
.i_wdata_read_end1(1'b1),
|
.i_wdata_read_end1(1'b1),
|
.o_wdata_ack1(),
|
.o_wdata_ack1(),
|
.o_strr1(w_rstr1),
|
.o_strr1(w_rstr1),
|
.o_dbr1(w_rdata1),
|
.o_dbr1(w_rdata1),
|
// port2 side Read Only
|
// port2 side Read Only
|
.i_req2(i_r_req2),
|
.i_req2(i_r_req2),
|
.i_add2(i_r_adrs2),
|
.i_add2(i_r_adrs2),
|
.i_len2(i_r_len2),
|
.i_len2(i_r_len2),
|
.o_cack2(w_cack2),
|
.o_cack2(w_cack2),
|
.o_strr2(o_r_rstr2),
|
.o_strr2(o_r_rstr2),
|
.o_dbr2(o_r_rdata2),
|
.o_dbr2(o_r_rdata2),
|
// port3 Write
|
// port3 Write
|
.i_req3(w_req3),
|
.i_req3(w_req3),
|
.i_add3(w_add3),
|
.i_add3(w_add3),
|
.i_len3(w_len3),
|
.i_len3(w_len3),
|
.i_be3(w_be3),
|
.i_be3(w_be3),
|
.o_cack3(w_cack3),
|
.o_cack3(w_cack3),
|
.i_strw3(w_strw3),
|
.i_strw3(w_strw3),
|
.i_dbw3(w_dbw3),
|
.i_dbw3(w_dbw3),
|
.i_wdata_read_end3(w_wdata_read_end3),
|
.i_wdata_read_end3(w_wdata_read_end3),
|
.o_wdata_ack3(w_wdata_ack3),
|
.o_wdata_ack3(w_wdata_ack3),
|
// output to bus bridge or
|
// output to bus bridge or
|
// memory bus arbiter far
|
// memory bus arbiter far
|
.o_breq(o_brg_req),
|
.o_breq(o_brg_req),
|
.o_bwe(o_brg_wr),
|
.o_bwe(o_brg_wr),
|
.o_bid(o_brg_id),
|
.o_bid(o_brg_id),
|
.o_badd(o_brg_adrs),
|
.o_badd(o_brg_adrs),
|
.o_blen(o_brg_len),
|
.o_blen(o_brg_len),
|
.i_back(i_brg_ack),
|
.i_back(i_brg_ack),
|
.o_bstrw(o_brg_wstr),
|
.o_bstrw(o_brg_wstr),
|
.o_bbe(o_brg_be),
|
.o_bbe(o_brg_be),
|
.o_bdbw(o_brg_wdata),
|
.o_bdbw(o_brg_wdata),
|
.i_backw(i_brg_wack),
|
.i_backw(i_brg_wack),
|
.i_bstrr(i_brg_rstr),
|
.i_bstrr(i_brg_rstr),
|
.i_blast(i_brg_rlast),
|
.i_blast(i_brg_rlast),
|
.i_brid(i_brg_rid),
|
.i_brid(i_brg_rid),
|
.i_bdbr(i_brg_rdata)
|
.i_bdbr(i_brg_rdata)
|
);
|
);
|
|
|
endmodule
|
endmodule
|
|
|