//=======================================================================
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//=======================================================================
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// Project Monophony
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// Project Monophony
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// Wire-Frame 3D Graphics Accelerator IP Core
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// Wire-Frame 3D Graphics Accelerator IP Core
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//
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//
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// File:
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// File:
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// fm_hsys.v
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// fm_hsys.v
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//
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//
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// Abstract:
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// Abstract:
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// System register module
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// System register module
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//
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//
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// Author:
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// Author:
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// Kenji Ishimaru (info.wf3d@gmail.com)
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// Kenji Ishimaru (info.info.wf3d@gmail.com)
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//
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//
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//======================================================================
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//======================================================================
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//
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//
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// Copyright (c) 2015, Kenji Ishimaru
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// Copyright (c) 2015, Kenji Ishimaru
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// All rights reserved.
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// All rights reserved.
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// modification, are permitted provided that the following conditions are met:
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//
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//
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// -Redistributions of source code must retain the above copyright notice,
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// -Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// this list of conditions and the following disclaimer.
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// -Redistributions in binary form must reproduce the above copyright notice,
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// -Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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// and/or other materials provided with the distribution.
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//
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//
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// Revision History
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// Revision History
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module fm_hsys (
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module fm_hsys (
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clk_core,
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clk_core,
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rst_x,
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rst_x,
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// internal interface
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// internal interface
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i_req,
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i_req,
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i_wr,
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i_wr,
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i_adrs,
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i_adrs,
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o_ack,
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o_ack,
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i_be,
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i_be,
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i_wd,
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i_wd,
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o_rstr,
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o_rstr,
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o_rd,
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o_rd,
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// configuration output
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// configuration output
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// Video controller
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// Video controller
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o_video_start,
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o_video_start,
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o_aa_en,
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o_aa_en,
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o_fb0_offset,
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o_fb0_offset,
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o_fb1_offset,
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o_fb1_offset,
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o_color_mode,
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o_color_mode,
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o_front_buffer,
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o_front_buffer,
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o_fb_blend_en,
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o_fb_blend_en,
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// status from Video controller
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// status from Video controller
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i_vint_x,
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i_vint_x,
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i_vint_edge,
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i_vint_edge,
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// status from 3D core
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// status from 3D core
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i_vtx_int,
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i_vtx_int,
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// int out
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// int out
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o_int
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o_int
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);
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);
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//////////////////////////////////
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//////////////////////////////////
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// I/O port definition
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// I/O port definition
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//////////////////////////////////
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//////////////////////////////////
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input clk_core;
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input clk_core;
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input rst_x;
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input rst_x;
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// internal interface
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// internal interface
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input i_req;
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input i_req;
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input i_wr;
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input i_wr;
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input [3:0] i_adrs;
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input [3:0] i_adrs;
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output o_ack;
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output o_ack;
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input [3:0] i_be;
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input [3:0] i_be;
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input [31:0] i_wd;
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input [31:0] i_wd;
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output o_rstr;
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output o_rstr;
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output [31:0] o_rd;
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output [31:0] o_rd;
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// configuration output
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// configuration output
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// Video controller
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// Video controller
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output o_video_start;
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output o_video_start;
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output [2:0] o_aa_en;
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output [2:0] o_aa_en;
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output [6:0] o_fb0_offset;
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output [6:0] o_fb0_offset;
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output [6:0] o_fb1_offset;
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output [6:0] o_fb1_offset;
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output [1:0] o_color_mode;
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output [1:0] o_color_mode;
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output o_front_buffer;
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output o_front_buffer;
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output o_fb_blend_en;
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output o_fb_blend_en;
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// status from Video controller
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// status from Video controller
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input i_vint_x;
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input i_vint_x;
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input i_vint_edge;
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input i_vint_edge;
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// status from 3D core
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// status from 3D core
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input i_vtx_int;
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input i_vtx_int;
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// int out
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// int out
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output reg o_int;
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output reg o_int;
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//////////////////////////////////
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//////////////////////////////////
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// regs
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// regs
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//////////////////////////////////
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//////////////////////////////////
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reg r_video_start;
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reg r_video_start;
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reg [2:0] r_aa_en;
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reg [2:0] r_aa_en;
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reg [6:0] r_fb0_offset;
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reg [6:0] r_fb0_offset;
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reg [6:0] r_fb1_offset;
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reg [6:0] r_fb1_offset;
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reg [1:0] r_color_mode;
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reg [1:0] r_color_mode;
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reg r_fb_blend_en;
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reg r_fb_blend_en;
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reg r_rstr;
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reg r_rstr;
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reg [31:0] r_rd;
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reg [31:0] r_rd;
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reg r_vint_x;
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reg r_vint_x;
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reg [2:0] r_mask;
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reg [2:0] r_mask;
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reg r_front_buffer;
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reg r_front_buffer;
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reg r_vint_clear;
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reg r_vint_clear;
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//////////////////////////////////
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//////////////////////////////////
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// wire
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// wire
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//////////////////////////////////
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//////////////////////////////////
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wire w_hit0;
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wire w_hit0;
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wire w_hit1;
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wire w_hit1;
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wire w_hit2;
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wire w_hit2;
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wire w_hit3;
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wire w_hit3;
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wire w_hit4;
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wire w_hit4;
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wire w_hit5;
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wire w_hit5;
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wire w_hit8;
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wire w_hit8;
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wire w_hit9;
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wire w_hit9;
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wire w_hitA;
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wire w_hitA;
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wire w_hitB;
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wire w_hitB;
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wire w_hitC;
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wire w_hitC;
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wire w_hitD;
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wire w_hitD;
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wire w_hitE;
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wire w_hitE;
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wire w_hitF;
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wire w_hitF;
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wire w_hit10;
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wire w_hit10;
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wire w_hit11;
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wire w_hit11;
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wire w_hit12;
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wire w_hit12;
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wire w_hit13;
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wire w_hit13;
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wire w_hit0_w;
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wire w_hit0_w;
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wire w_hit1_w;
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wire w_hit1_w;
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wire w_hit2_w;
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wire w_hit2_w;
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wire w_hit3_w;
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wire w_hit3_w;
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wire w_hit4_w;
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wire w_hit4_w;
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wire w_hit5_w;
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wire w_hit5_w;
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wire w_hit9_w;
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wire w_hit9_w;
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wire w_hitA_w;
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wire w_hitA_w;
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wire w_hitB_w;
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wire w_hitB_w;
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wire [31:0] w_rd;
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wire [31:0] w_rd;
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wire w_rstr;
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wire w_rstr;
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wire w_vint_x;
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wire w_vint_x;
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wire w_vint_on;
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wire w_vint_on;
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wire [2:0] w_int;
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wire [2:0] w_int;
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//////////////////////////////////
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//////////////////////////////////
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// assign
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// assign
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//////////////////////////////////
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//////////////////////////////////
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assign w_hit0 = (i_adrs[3:0] == 4'h0); // 0
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assign w_hit0 = (i_adrs[3:0] == 4'h0); // 0
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assign w_hit1 = (i_adrs[3:0] == 4'h1); // 4
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assign w_hit1 = (i_adrs[3:0] == 4'h1); // 4
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assign w_hit2 = (i_adrs[3:0] == 4'h2); // 8
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assign w_hit2 = (i_adrs[3:0] == 4'h2); // 8
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assign w_hit3 = (i_adrs[3:0] == 4'h3); // c
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assign w_hit3 = (i_adrs[3:0] == 4'h3); // c
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assign w_hit4 = (i_adrs[3:0] == 4'h4); // 10
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assign w_hit4 = (i_adrs[3:0] == 4'h4); // 10
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assign w_hit5 = (i_adrs[3:0] == 4'h5); // 14
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assign w_hit5 = (i_adrs[3:0] == 4'h5); // 14
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assign w_hit8 = (i_adrs[3:0] == 4'h8); // 20
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assign w_hit8 = (i_adrs[3:0] == 4'h8); // 20
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assign w_hit9 = (i_adrs[3:0] == 4'h9); // 24
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assign w_hit9 = (i_adrs[3:0] == 4'h9); // 24
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assign w_hitA = (i_adrs[3:0] == 4'ha); // 28
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assign w_hitA = (i_adrs[3:0] == 4'ha); // 28
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assign w_hitB = (i_adrs[3:0] == 4'hb); // 2c
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assign w_hitB = (i_adrs[3:0] == 4'hb); // 2c
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assign w_hit0_w = w_hit0 & i_wr & i_req;
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assign w_hit0_w = w_hit0 & i_wr & i_req;
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assign w_hit1_w = w_hit1 & i_wr & i_req;
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assign w_hit1_w = w_hit1 & i_wr & i_req;
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assign w_hit2_w = w_hit2 & i_wr & i_req;
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assign w_hit2_w = w_hit2 & i_wr & i_req;
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assign w_hit3_w = w_hit3 & i_wr & i_req;
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assign w_hit3_w = w_hit3 & i_wr & i_req;
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assign w_hit4_w = w_hit4 & i_wr & i_req;
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assign w_hit4_w = w_hit4 & i_wr & i_req;
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assign w_hit5_w = w_hit5 & i_wr & i_req;
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assign w_hit5_w = w_hit5 & i_wr & i_req;
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assign w_hit9_w = w_hit9 & i_wr & i_req;
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assign w_hit9_w = w_hit9 & i_wr & i_req;
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assign w_hitA_w = w_hitA & i_wr & i_req;
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assign w_hitA_w = w_hitA & i_wr & i_req;
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assign w_hitB_w = w_hitB & i_wr & i_req;
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assign w_hitB_w = w_hitB & i_wr & i_req;
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assign w_rstr = i_req & !i_wr;
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assign w_rstr = i_req & !i_wr;
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assign w_rd = (w_hit0) ? {16'hbeef,5'b0,r_aa_en,7'b0,r_video_start} :
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assign w_rd = (w_hit0) ? {16'hbeef,5'b0,r_aa_en,7'b0,r_video_start} :
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(w_hit1) ? {6'b0,r_fb0_offset,19'b0} :
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(w_hit1) ? {6'b0,r_fb0_offset,19'b0} :
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(w_hit2) ? {6'b0,r_fb1_offset,19'b0} :
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(w_hit2) ? {6'b0,r_fb1_offset,19'b0} :
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(w_hit5) ? {30'b0,r_color_mode} :
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(w_hit5) ? {30'b0,r_color_mode} :
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(w_hit8) ? {29'b0,i_vtx_int,!i_vint_x,!r_vint_x} :
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(w_hit8) ? {29'b0,i_vtx_int,!i_vint_x,!r_vint_x} :
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(w_hit9) ? {31'b0,r_vint_clear} :
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(w_hit9) ? {31'b0,r_vint_clear} :
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(w_hitA) ? {29'b0,r_mask} :
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(w_hitA) ? {29'b0,r_mask} :
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{31'b0,r_front_buffer};
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{31'b0,r_front_buffer};
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assign w_vint_on = i_vint_edge; // falling edge detect
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assign w_vint_on = i_vint_edge; // falling edge detect
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assign w_vint_x = ~r_vint_clear | i_vint_x;
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assign w_vint_x = ~r_vint_clear | i_vint_x;
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assign w_int[0] = (r_mask[0]) ? 1'b0 : ~r_vint_x;
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assign w_int[0] = (r_mask[0]) ? 1'b0 : ~r_vint_x;
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assign w_int[1] = 1'b0;
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assign w_int[1] = 1'b0;
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assign w_int[2] = (r_mask[2]) ? 1'b0 : i_vtx_int;
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assign w_int[2] = (r_mask[2]) ? 1'b0 : i_vtx_int;
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assign o_rstr = r_rstr;
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assign o_rstr = r_rstr;
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assign o_rd = r_rd;
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assign o_rd = r_rd;
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assign o_ack = i_req;
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assign o_ack = i_req;
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assign o_video_start = r_video_start;
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assign o_video_start = r_video_start;
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assign o_aa_en = r_aa_en;
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assign o_aa_en = r_aa_en;
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assign o_fb0_offset = r_fb0_offset;
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assign o_fb0_offset = r_fb0_offset;
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assign o_fb1_offset = r_fb1_offset;
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assign o_fb1_offset = r_fb1_offset;
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assign o_color_mode = r_color_mode;
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assign o_color_mode = r_color_mode;
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assign o_front_buffer = r_front_buffer;
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assign o_front_buffer = r_front_buffer;
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assign o_fb_blend_en = r_fb_blend_en;
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assign o_fb_blend_en = r_fb_blend_en;
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//////////////////////////////////
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//////////////////////////////////
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// always
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// always
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//////////////////////////////////
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//////////////////////////////////
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always @(posedge clk_core or negedge rst_x) begin
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always @(posedge clk_core or negedge rst_x) begin
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if (~rst_x) begin
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if (~rst_x) begin
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r_video_start <= 1'b0;
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r_video_start <= 1'b0;
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end else begin
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end else begin
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if (w_hit0_w) begin
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if (w_hit0_w) begin
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if (i_be[0]) r_video_start <= i_wd[0];
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if (i_be[0]) r_video_start <= i_wd[0];
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if (i_be[1]) r_aa_en <= i_wd[10:8];
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if (i_be[1]) r_aa_en <= i_wd[10:8];
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if (i_be[2]) r_fb_blend_en <= i_wd[16];
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if (i_be[2]) r_fb_blend_en <= i_wd[16];
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end
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end
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end
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end
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end
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end
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// register holds 32-bit address
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// register holds 32-bit address
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always @(posedge clk_core or negedge rst_x) begin
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always @(posedge clk_core or negedge rst_x) begin
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if (~rst_x) begin
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if (~rst_x) begin
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r_fb0_offset <= 7'b0;
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r_fb0_offset <= 7'b0;
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end else begin
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end else begin
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if (w_hit1_w) begin
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if (w_hit1_w) begin
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if (i_be[2]) r_fb0_offset[4:0] <= i_wd[23:19];
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if (i_be[2]) r_fb0_offset[4:0] <= i_wd[23:19];
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if (i_be[3]) r_fb0_offset[6:5] <= i_wd[25:24];
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if (i_be[3]) r_fb0_offset[6:5] <= i_wd[25:24];
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end
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end
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end
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end
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end
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end
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always @(posedge clk_core or negedge rst_x) begin
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always @(posedge clk_core or negedge rst_x) begin
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if (~rst_x) begin
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if (~rst_x) begin
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r_fb1_offset <= 7'b0;
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r_fb1_offset <= 7'b0;
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end else begin
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end else begin
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if (w_hit2_w) begin
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if (w_hit2_w) begin
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if (i_be[2]) r_fb1_offset[4:0] <= i_wd[23:19];
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if (i_be[2]) r_fb1_offset[4:0] <= i_wd[23:19];
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if (i_be[3]) r_fb1_offset[6:5] <= i_wd[25:24];
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if (i_be[3]) r_fb1_offset[6:5] <= i_wd[25:24];
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end
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end
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end
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end
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end
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end
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|
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always @(posedge clk_core or negedge rst_x) begin
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always @(posedge clk_core or negedge rst_x) begin
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if (~rst_x) begin
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if (~rst_x) begin
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r_color_mode <= 2'b0;
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r_color_mode <= 2'b0;
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end else begin
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end else begin
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if (w_hit5_w) begin
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if (w_hit5_w) begin
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if (i_be[0]) r_color_mode <= i_wd[1:0];
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if (i_be[0]) r_color_mode <= i_wd[1:0];
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end
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end
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end
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end
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end
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end
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|
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always @(posedge clk_core or negedge rst_x) begin
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always @(posedge clk_core or negedge rst_x) begin
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if (~rst_x) begin
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if (~rst_x) begin
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r_vint_clear <= 1'b0;
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r_vint_clear <= 1'b0;
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end else begin
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end else begin
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if (w_hit9_w) begin
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if (w_hit9_w) begin
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if (i_be[0]) r_vint_clear <= i_wd[0];
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if (i_be[0]) r_vint_clear <= i_wd[0];
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end else if (w_vint_on) begin
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end else if (w_vint_on) begin
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r_vint_clear <= 1'b1;
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r_vint_clear <= 1'b1;
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end
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end
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end
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end
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end
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end
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|
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always @(posedge clk_core or negedge rst_x) begin
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always @(posedge clk_core or negedge rst_x) begin
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if (~rst_x) begin
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if (~rst_x) begin
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r_mask <= 2'b11;
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r_mask <= 2'b11;
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end else begin
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end else begin
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if (w_hitA_w) begin
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if (w_hitA_w) begin
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if (i_be[0]) r_mask <= i_wd[1:0];
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if (i_be[0]) r_mask <= i_wd[1:0];
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end
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end
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end
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end
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end
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end
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|
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always @(posedge clk_core or negedge rst_x) begin
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always @(posedge clk_core or negedge rst_x) begin
|
if (~rst_x) begin
|
if (~rst_x) begin
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r_front_buffer <= 1'b0;
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r_front_buffer <= 1'b0;
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end else begin
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end else begin
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if (w_hitB_w) begin
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if (w_hitB_w) begin
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if (i_be[0]) r_front_buffer <= i_wd[0];
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if (i_be[0]) r_front_buffer <= i_wd[0];
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end
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end
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end
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end
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end
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end
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|
|
|
|
always @(posedge clk_core) begin
|
always @(posedge clk_core) begin
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r_rd <= w_rd;
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r_rd <= w_rd;
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end
|
end
|
|
|
always @(posedge clk_core or negedge rst_x) begin
|
always @(posedge clk_core or negedge rst_x) begin
|
if (~rst_x) begin
|
if (~rst_x) begin
|
r_rstr <= 1'b0;
|
r_rstr <= 1'b0;
|
end else begin
|
end else begin
|
r_rstr <= w_rstr;
|
r_rstr <= w_rstr;
|
end
|
end
|
end
|
end
|
|
|
|
|
always @(posedge clk_core or negedge rst_x) begin
|
always @(posedge clk_core or negedge rst_x) begin
|
if (~rst_x) begin
|
if (~rst_x) begin
|
r_vint_x <= 1'b1;
|
r_vint_x <= 1'b1;
|
end else begin
|
end else begin
|
r_vint_x <= w_vint_x;
|
r_vint_x <= w_vint_x;
|
end
|
end
|
end
|
end
|
|
|
always @(posedge clk_core or negedge rst_x) begin
|
always @(posedge clk_core or negedge rst_x) begin
|
if (~rst_x) begin
|
if (~rst_x) begin
|
o_int <= 1'b0;
|
o_int <= 1'b0;
|
end else begin
|
end else begin
|
o_int <= |w_int;
|
o_int <= |w_int;
|
end
|
end
|
end
|
end
|
|
|
endmodule
|
endmodule
|
|
|