//=======================================================================
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//=======================================================================
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// Project Monophony
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// Project Monophony
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// Wire-Frame 3D Graphics Accelerator IP Core
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// Wire-Frame 3D Graphics Accelerator IP Core
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//
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//
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// File:
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// File:
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// fm_hvc_data.v
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// fm_hvc_data.v
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//
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//
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// Abstract:
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// Abstract:
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// LCD output color data construction
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// LCD output color data construction
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//
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//
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// Author:
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// Author:
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// Kenji Ishimaru (info.wf3d@gmail.com)
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// Kenji Ishimaru (info.info.wf3d@gmail.com)
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//
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//
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//======================================================================
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//======================================================================
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//
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//
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// Copyright (c) 2015, Kenji Ishimaru
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// Copyright (c) 2015, Kenji Ishimaru
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// All rights reserved.
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// All rights reserved.
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// modification, are permitted provided that the following conditions are met:
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//
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//
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// -Redistributions of source code must retain the above copyright notice,
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// -Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// this list of conditions and the following disclaimer.
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// -Redistributions in binary form must reproduce the above copyright notice,
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// -Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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// and/or other materials provided with the distribution.
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//
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//
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// Revision History
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// Revision History
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module fm_hvc_data (
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module fm_hvc_data (
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clk_core,
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clk_core,
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clk_vi,
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clk_vi,
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rst_x,
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rst_x,
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// sdram interface
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// sdram interface
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i_rstr,
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i_rstr,
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i_rd,
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i_rd,
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// timing input
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// timing input
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i_h_active,
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i_h_active,
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i_first_line,
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i_first_line,
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i_hsync,
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i_hsync,
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i_vsync,
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i_vsync,
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o_fifo_available,
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o_fifo_available,
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i_fifo_available_ack,
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i_fifo_available_ack,
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// configuration
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// configuration
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i_video_start,
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i_video_start,
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i_color_mode,
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i_color_mode,
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// test color input
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// test color input
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i_test_r,
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i_test_r,
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i_test_g,
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i_test_g,
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i_test_b,
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i_test_b,
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// color out
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// color out
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o_r,
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o_r,
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o_g,
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o_g,
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o_b,
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o_b,
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o_a
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o_a
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);
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);
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//////////////////////////////////
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//////////////////////////////////
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// I/O port definition
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// I/O port definition
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//////////////////////////////////
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//////////////////////////////////
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input clk_core;
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input clk_core;
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input clk_vi; // 25MHz
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input clk_vi; // 25MHz
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input rst_x;
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input rst_x;
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// sdram interface
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// sdram interface
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input i_rstr;
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input i_rstr;
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`ifdef PP_BUSWIDTH_64
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`ifdef PP_BUSWIDTH_64
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input [63:0] i_rd;
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input [63:0] i_rd;
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`else
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`else
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input [31:0] i_rd;
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input [31:0] i_rd;
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`endif
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`endif
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// timing input
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// timing input
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input i_h_active;
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input i_h_active;
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input i_first_line;
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input i_first_line;
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input i_hsync;
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input i_hsync;
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input i_vsync;
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input i_vsync;
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output o_fifo_available;
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output o_fifo_available;
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input i_fifo_available_ack;
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input i_fifo_available_ack;
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// configuration
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// configuration
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input i_video_start;
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input i_video_start;
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input [1:0] i_color_mode;
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input [1:0] i_color_mode;
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// test color input
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// test color input
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input [7:0] i_test_r;
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input [7:0] i_test_r;
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input [7:0] i_test_g;
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input [7:0] i_test_g;
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input [7:0] i_test_b;
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input [7:0] i_test_b;
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output [7:0] o_r;
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output [7:0] o_r;
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output [7:0] o_g;
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output [7:0] o_g;
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output [7:0] o_b;
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output [7:0] o_b;
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output [7:0] o_a;
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output [7:0] o_a;
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//////////////////////////////////
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//////////////////////////////////
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// reg
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// reg
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//////////////////////////////////
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//////////////////////////////////
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reg [9:0] r_pix_cnt;
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reg [9:0] r_pix_cnt;
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reg r_fifo_available;
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reg r_fifo_available;
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reg [7:0] r_r;
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reg [7:0] r_r;
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reg [7:0] r_g;
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reg [7:0] r_g;
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reg [7:0] r_b;
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reg [7:0] r_b;
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reg [7:0] r_r_neg;
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reg [7:0] r_r_neg;
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reg [7:0] r_g_neg;
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reg [7:0] r_g_neg;
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reg [7:0] r_b_neg;
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reg [7:0] r_b_neg;
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reg r_fifo_available_ack_1z;
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reg r_fifo_available_ack_1z;
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reg r_fifo_available_ack_2z;
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reg r_fifo_available_ack_2z;
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reg r_fifo_available_ack_3z;
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reg r_fifo_available_ack_3z;
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//////////////////////////////////
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//////////////////////////////////
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// wire
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// wire
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//////////////////////////////////
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//////////////////////////////////
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wire w_rstr_base;
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wire w_rstr_base;
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wire w_rstr_upper;
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wire w_rstr_upper;
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wire [15:0] w_di;
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wire [15:0] w_di;
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wire [31:0] w_do;
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wire [31:0] w_do;
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wire [31:0] w_do_normal;
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wire [31:0] w_do_normal;
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wire [7:0] w_r_aa;
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wire [7:0] w_r_aa;
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wire [7:0] w_g_aa;
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wire [7:0] w_g_aa;
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wire [7:0] w_b_aa;
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wire [7:0] w_b_aa;
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wire [7:0] w_r_f;
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wire [7:0] w_r_f;
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wire [7:0] w_g_f;
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wire [7:0] w_g_f;
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wire [7:0] w_b_f;
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wire [7:0] w_b_f;
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wire [7:0] w_r;
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wire [7:0] w_r;
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wire [7:0] w_g;
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wire [7:0] w_g;
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wire [7:0] w_b;
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wire [7:0] w_b;
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wire w_ren;
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wire w_ren;
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wire w_fifo_reset_x;
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wire w_fifo_reset_x;
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wire w_fifo_available_ack_rise;
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wire w_fifo_available_ack_rise;
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wire w_pix_av_c0;
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wire w_pix_av_c0;
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wire w_pix_av_c2;
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wire w_pix_av_c2;
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wire w_pix_av_c3;
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wire w_pix_av_c3;
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//////////////////////////////////
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//////////////////////////////////
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// assign
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// assign
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//////////////////////////////////
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//////////////////////////////////
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assign w_fifo_available_ack_rise = r_fifo_available_ack_2z &
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assign w_fifo_available_ack_rise = r_fifo_available_ack_2z &
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!r_fifo_available_ack_3z;
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!r_fifo_available_ack_3z;
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assign w_fifo_reset_x = i_vsync & rst_x;
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assign w_fifo_reset_x = i_vsync & rst_x;
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assign w_rstr_base = i_rstr;
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assign w_rstr_base = i_rstr;
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assign w_rstr_upper = i_rstr;
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assign w_rstr_upper = i_rstr;
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assign w_ren = i_h_active;
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assign w_ren = i_h_active;
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assign w_r_f = w_do_normal[31:24];
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assign w_r_f = w_do_normal[31:24];
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assign w_g_f = w_do_normal[23:16];
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assign w_g_f = w_do_normal[23:16];
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assign w_b_f = w_do_normal[15:8];
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assign w_b_f = w_do_normal[15:8];
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assign w_do_normal = f_get_color(w_di,i_color_mode);
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assign w_do_normal = f_get_color(w_di,i_color_mode);
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assign w_b = (!i_video_start) ? i_test_b :
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assign w_b = (!i_video_start) ? i_test_b :
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(i_h_active )? w_b_f :
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(i_h_active )? w_b_f :
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8'h00;
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8'h00;
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assign w_g = (!i_video_start) ? i_test_g :
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assign w_g = (!i_video_start) ? i_test_g :
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(i_h_active )? w_g_f :
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(i_h_active )? w_g_f :
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8'h00;
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8'h00;
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assign w_r = (!i_video_start) ? i_test_r :
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assign w_r = (!i_video_start) ? i_test_r :
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(i_h_active )? w_r_f :
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(i_h_active )? w_r_f :
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8'h00;
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8'h00;
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assign o_b = r_b; //r_b_neg
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assign o_b = r_b; //r_b_neg
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assign o_g = r_g; // r_g_neg
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assign o_g = r_g; // r_g_neg
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assign o_r = r_r; // r_r_neg
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assign o_r = r_r; // r_r_neg
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assign o_fifo_available = r_fifo_available;
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assign o_fifo_available = r_fifo_available;
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assign w_pix_av_c0 = ((i_color_mode == 'd0)&(r_pix_cnt == 'd63));
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assign w_pix_av_c0 = ((i_color_mode == 'd0)&(r_pix_cnt == 'd63));
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assign w_pix_av_c2 = ((i_color_mode == 'd2)&(r_pix_cnt == 'd127));
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assign w_pix_av_c2 = ((i_color_mode == 'd2)&(r_pix_cnt == 'd127));
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assign w_pix_av_c3 = ((i_color_mode == 'd3)&(r_pix_cnt == 'd255));
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assign w_pix_av_c3 = ((i_color_mode == 'd3)&(r_pix_cnt == 'd255));
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//////////////////////////////////
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//////////////////////////////////
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// always
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// always
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//////////////////////////////////
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//////////////////////////////////
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always @(posedge clk_vi or negedge rst_x) begin
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always @(posedge clk_vi or negedge rst_x) begin
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if (~rst_x) begin
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if (~rst_x) begin
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r_pix_cnt <= 10'd0;
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r_pix_cnt <= 10'd0;
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end else begin
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end else begin
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if (~i_hsync) r_pix_cnt <= 10'd0;
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if (~i_hsync) r_pix_cnt <= 10'd0;
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else if (w_pix_av_c0|w_pix_av_c2|w_pix_av_c3)r_pix_cnt <= 10'd0;
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else if (w_pix_av_c0|w_pix_av_c2|w_pix_av_c3)r_pix_cnt <= 10'd0;
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else if (w_ren) r_pix_cnt <= r_pix_cnt + 1'b1;
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else if (w_ren) r_pix_cnt <= r_pix_cnt + 1'b1;
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end
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end
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end
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end
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always @(posedge clk_vi or negedge rst_x) begin
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always @(posedge clk_vi or negedge rst_x) begin
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if (~rst_x) begin
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if (~rst_x) begin
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r_fifo_available <= 1'b0;
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r_fifo_available <= 1'b0;
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end else begin
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end else begin
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if (w_pix_av_c0|w_pix_av_c2|w_pix_av_c3) r_fifo_available <= 1'b1; // 32 x 2
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if (w_pix_av_c0|w_pix_av_c2|w_pix_av_c3) r_fifo_available <= 1'b1; // 32 x 2
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else if (~i_hsync | w_fifo_available_ack_rise) r_fifo_available <= 1'b0;
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else if (~i_hsync | w_fifo_available_ack_rise) r_fifo_available <= 1'b0;
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end
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end
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end
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end
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always @(posedge clk_vi or negedge rst_x) begin
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always @(posedge clk_vi or negedge rst_x) begin
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if (~rst_x) begin
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if (~rst_x) begin
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r_fifo_available_ack_1z <= 1'b0;
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r_fifo_available_ack_1z <= 1'b0;
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r_fifo_available_ack_2z <= 1'b0;
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r_fifo_available_ack_2z <= 1'b0;
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r_fifo_available_ack_3z <= 1'b0;
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r_fifo_available_ack_3z <= 1'b0;
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end else begin
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end else begin
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r_fifo_available_ack_1z <= i_fifo_available_ack;
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r_fifo_available_ack_1z <= i_fifo_available_ack;
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r_fifo_available_ack_2z <= r_fifo_available_ack_1z;
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r_fifo_available_ack_2z <= r_fifo_available_ack_1z;
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r_fifo_available_ack_3z <= r_fifo_available_ack_2z;
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r_fifo_available_ack_3z <= r_fifo_available_ack_2z;
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end
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end
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end
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end
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always @(posedge clk_vi) begin
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always @(posedge clk_vi) begin
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r_r <= w_r;
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r_r <= w_r;
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r_g <= w_g;
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r_g <= w_g;
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r_b <= w_b;
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r_b <= w_b;
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end
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end
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//////////////////////////////////
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//////////////////////////////////
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// function
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// function
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//////////////////////////////////
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//////////////////////////////////
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function [31:0] f_get_color;
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function [31:0] f_get_color;
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input [15:0] idata;
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input [15:0] idata;
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input [1:0] mode;
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input [1:0] mode;
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reg [7:0] r;
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reg [7:0] r;
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reg [7:0] g;
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reg [7:0] g;
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reg [7:0] b;
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reg [7:0] b;
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reg [7:0] a;
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reg [7:0] a;
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begin
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begin
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case (mode)
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case (mode)
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2'b00 : begin
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2'b00 : begin
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// color mode 5:6:5
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// color mode 5:6:5
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r = {idata[15:11],idata[15:13]};
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r = {idata[15:11],idata[15:13]};
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g = {idata[10:5],idata[10:9]};
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g = {idata[10:5],idata[10:9]};
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b = {idata[4:0],idata[4:2]};
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b = {idata[4:0],idata[4:2]};
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a = 8'h0;
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a = 8'h0;
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end
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end
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2'b01 : begin
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2'b01 : begin
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// color mode 5:5:5:1
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// color mode 5:5:5:1
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r = {idata[15:11],idata[15:13]};
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r = {idata[15:11],idata[15:13]};
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g = {idata[10:6],idata[10:8]};
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g = {idata[10:6],idata[10:8]};
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b = {idata[5:1],idata[5:3]};
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b = {idata[5:1],idata[5:3]};
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a = {idata[0],7'b0};
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a = {idata[0],7'b0};
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end
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end
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2'b10 : begin
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2'b10 : begin
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// color mode 2:3:3
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// color mode 2:3:3
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r = {'d4{idata[7:6]}};
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r = {'d4{idata[7:6]}};
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g = {idata[5:3],idata[5:3],idata[5:4]};
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g = {idata[5:3],idata[5:3],idata[5:4]};
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b = {idata[2:0],idata[2:0],idata[2:1]};
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b = {idata[2:0],idata[2:0],idata[2:1]};
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a = 8'h0;
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a = 8'h0;
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end
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end
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default : begin
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default : begin
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// color mode 1:2:2
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// color mode 1:2:2
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r = {'d8{idata[3]}};
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r = {'d8{idata[3]}};
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g = {'d4{idata[2:1]}};
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g = {'d4{idata[2:1]}};
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b = {'d8{idata[0]}};
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b = {'d8{idata[0]}};
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a = 8'h0;
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a = 8'h0;
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end
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end
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endcase
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endcase
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f_get_color = {r,g,b,a};
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f_get_color = {r,g,b,a};
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end
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end
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endfunction
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endfunction
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//////////////////////////////////
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//////////////////////////////////
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// module instance
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// module instance
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//////////////////////////////////
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//////////////////////////////////
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// 32bit x 128 entry fifo for current line
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// 32bit x 128 entry fifo for current line
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fm_afifo fm_afifo_c (
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fm_afifo fm_afifo_c (
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.clk_core(clk_core),
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.clk_core(clk_core),
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.clk_vi(clk_vi),
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.clk_vi(clk_vi),
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.rst_x(w_fifo_reset_x),
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.rst_x(w_fifo_reset_x),
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.i_color_mode(i_color_mode),
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.i_color_mode(i_color_mode),
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.i_wstrobe(w_rstr_base),
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.i_wstrobe(w_rstr_base),
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.i_dt(i_rd),
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.i_dt(i_rd),
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.o_full(),
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.o_full(),
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.i_renable(w_ren),
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.i_renable(w_ren),
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.o_dt(w_di),
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.o_dt(w_di),
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.o_empty(),
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.o_empty(),
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.o_dnum()
|
.o_dnum()
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);
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);
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endmodule
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endmodule
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