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//
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//
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// Abstract:
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// Abstract:
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// VGA LCD Controller DMAC
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// VGA LCD Controller DMAC
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//
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//
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// Author:
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// Author:
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// Kenji Ishimaru (kenji.ishimaru@prtissimo.com)
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// Kenji Ishimaru (info.wf3d@gmail.com)
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//
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//
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//======================================================================
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//======================================================================
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//
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//
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// Copyright (c) 2015, Kenji Ishimaru
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// Copyright (c) 2015, Kenji Ishimaru
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// All rights reserved.
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// All rights reserved.
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i_color_mode,
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i_color_mode,
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i_video_start,
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i_video_start,
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i_vsync,
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i_vsync,
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i_hsync,
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i_hsync,
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i_fb0_offset,
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i_fb0_offset,
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i_fb0_ms_offset,
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i_fb1_offset,
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i_fb1_offset,
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i_fb1_ms_offset,
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i_front_buffer,
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i_front_buffer,
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i_aa_en,
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i_fifo_available,
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i_fifo_available,
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o_fifo_available_ack,
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o_fifo_available_ack,
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o_vsync,
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o_vsync,
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o_vsync_edge,
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o_vsync_edge,
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// dram if
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// dram if
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);
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);
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////////////////////////////
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////////////////////////////
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// Parameter definition
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// Parameter definition
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////////////////////////////
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////////////////////////////
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parameter P_IDLE = 3'd0;
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parameter P_IB_ADDR_WIDTH ='d24;
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parameter P_REQ = 3'd1;
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parameter P_IB_LEN_WIDTH = 'd6;
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parameter P_REQ_AA = 3'd2;
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parameter P_WAIT_FIFO_AVL = 3'd3;
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parameter P_WAIT_AVL_FALL = 3'd4;
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parameter P_BURST_SIZE = 6'd32;
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localparam P_IDLE = 3'd0;
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parameter P_BURST_SIZE_H = 6'd16;
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localparam P_REQ = 3'd1;
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localparam P_REQ_AA = 3'd2;
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localparam P_WAIT_FIFO_AVL = 3'd3;
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localparam P_WAIT_AVL_FALL = 3'd4;
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`ifdef PP_BUSWIDTH_64
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localparam P_BURST_SIZE = 6'd16;
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localparam P_BURST_SIZE_H = 6'd8;
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`else
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localparam P_BURST_SIZE = 6'd32;
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localparam P_BURST_SIZE_H = 6'd16;
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`endif
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//////////////////////////////////
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//////////////////////////////////
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// I/O port definition
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// I/O port definition
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//////////////////////////////////
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//////////////////////////////////
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input clk_core;
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input clk_core;
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input rst_x;
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input rst_x;
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input [1:0] i_color_mode;
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input [1:0] i_color_mode;
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input i_video_start;
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input i_video_start;
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input i_vsync;
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input i_vsync;
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input i_hsync;
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input i_hsync;
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`ifdef PP_BUSWIDTH_64
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input [11:0] i_fb0_offset;
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input [11:0] i_fb1_offset;
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`else
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input [6:0] i_fb0_offset;
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input [6:0] i_fb0_offset;
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input [3:0] i_fb0_ms_offset;
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input [6:0] i_fb1_offset;
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input [6:0] i_fb1_offset;
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input [3:0] i_fb1_ms_offset;
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`endif
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input i_front_buffer;
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input i_front_buffer;
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input i_aa_en;
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input i_fifo_available;
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input i_fifo_available;
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output o_fifo_available_ack;
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output o_fifo_available_ack;
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output o_vsync;
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output o_vsync;
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output o_vsync_edge;
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output o_vsync_edge;
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// dram if
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// dram if
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output o_req;
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output o_req;
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output [23:0] o_adrs;
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output [P_IB_ADDR_WIDTH-1:0]
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output [5:0] o_len; // 32 burst x 10
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o_adrs;
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output [P_IB_LEN_WIDTH-1:0]
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o_len; // 32 burst x 10
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input i_ack;
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input i_ack;
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//////////////////////////////////
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//////////////////////////////////
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// reg
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// reg
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//////////////////////////////////
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//////////////////////////////////
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reg [2:0] r_state;
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reg [2:0] r_state;
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reg r_req;
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reg r_req;
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// reg [13:0] r_cur_adrs_l;
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`ifdef PP_BUSWIDTH_64
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reg [13:0] r_cur_adrs_l;
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`else
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reg [12:0] r_cur_adrs_l;
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reg [12:0] r_cur_adrs_l;
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`endif
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reg [3:0] r_req_cnt;
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reg [3:0] r_req_cnt;
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// syncro register
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// syncro register
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reg r_vsync_1z;
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reg r_vsync_1z;
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reg r_vsync_2z;
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reg r_vsync_2z;
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reg r_vsync_3z;
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reg r_vsync_3z;
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Line 140... |
wire w_h_start;
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wire w_h_start;
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wire w_adrs_inc;
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wire w_adrs_inc;
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wire w_line_end;
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wire w_line_end;
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wire w_req_cnt_clear;
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wire w_req_cnt_clear;
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`ifdef PP_BUSWIDTH_64
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wire [11:0] w_fb_offset;
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wire [11:0] w_offset;
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`else
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wire [6:0] w_fb_offset;
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wire [6:0] w_fb_offset;
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wire [6:0] w_fb_ms_offset;
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wire [6:0] w_offset;
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wire [6:0] w_offset;
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`endif
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wire w_hburst;
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wire w_hburst;
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//////////////////////////////////
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//////////////////////////////////
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// assign
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// assign
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//////////////////////////////////
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//////////////////////////////////
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assign o_req = r_req;
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assign o_req = r_req;
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assign w_hburst = (i_color_mode == 2'd3)&(r_req_cnt == 4'd2);
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assign w_hburst = (i_color_mode == 2'd3)&(r_req_cnt == 4'd2);
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assign o_len = (w_hburst) ? P_BURST_SIZE_H : P_BURST_SIZE;
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assign o_len = (w_hburst) ? P_BURST_SIZE_H : P_BURST_SIZE;
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assign o_fifo_available_ack = r_fifo_available_ack;
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assign o_fifo_available_ack = r_fifo_available_ack;
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assign w_set_initial_adrs = w_v_rise;
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assign w_set_initial_adrs = w_v_rise;
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assign w_adrs_inc = (i_aa_en) ? (r_state == P_REQ_AA) & i_ack:
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assign w_adrs_inc = (r_state == P_REQ) & i_ack;
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(r_state == P_REQ) & i_ack;
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assign w_h_start = i_video_start & r_hsync_2z & !r_hsync_3z; // rise of hsync
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assign w_h_start = i_video_start & r_hsync_2z & !r_hsync_3z; // rise of hsync
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assign w_v_rise = r_vsync_2z & !r_vsync_3z; // rising edge of vsync
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assign w_v_rise = r_vsync_2z & !r_vsync_3z; // rising edge of vsync
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assign w_line_end = (i_color_mode == 2'd3) ? (r_req_cnt == 4'd3) :// 80 times:
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assign w_line_end = (i_color_mode == 2'd3) ? (r_req_cnt == 4'd3) :// 80 times, 32burstx2, 16burstx1
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(i_color_mode == 2'd2) ? (r_req_cnt == 4'd5) :// 160 times
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(i_color_mode == 2'd2) ? (r_req_cnt == 4'd5) :// 160 times, 32burstx5
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(r_req_cnt == 4'd10); // 320 times
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(r_req_cnt == 4'd10); // 320 times, 32burstx10
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// 80 times, 16burstx2, 8burstx1 (64)
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assign w_req_cnt_clear = (w_line_end & !r_fifo_available_2z &
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assign w_req_cnt_clear = (w_line_end & !r_fifo_available_2z &
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(r_state == P_WAIT_AVL_FALL)) |
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(r_state == P_WAIT_AVL_FALL)) |
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(w_line_end & (r_state == P_WAIT_FIFO_AVL) & (i_color_mode == 'd3));
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(w_line_end & (r_state == P_WAIT_FIFO_AVL) & (i_color_mode == 'd3));
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// assign o_adrs = {w_offset, r_cur_adrs_l,4'b0}; // w_offset[21:18]
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`ifdef PP_BUSWIDTH_64
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assign o_adrs = {w_offset,r_cur_adrs_l,4'b0}; // w_offset[23:17]
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assign o_adrs = {w_offset, r_cur_adrs_l,3'b0};
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`else
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assign o_adrs = {w_offset, r_cur_adrs_l,4'b0};
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`endif
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assign w_fb_offset = (i_front_buffer) ? i_fb1_offset : i_fb0_offset;
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assign w_fb_offset = (i_front_buffer) ? i_fb1_offset : i_fb0_offset;
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assign w_fb_ms_offset = (i_front_buffer) ? i_fb1_ms_offset : i_fb0_ms_offset;
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assign w_offset = w_fb_offset;
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assign w_offset = (r_state == P_REQ_AA) ? w_fb_ms_offset : w_fb_offset;
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assign o_vsync = r_vsync_2z;
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assign o_vsync = r_vsync_2z;
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assign o_vsync_edge = !r_vsync_2z & r_vsync_3z; // falling edge
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assign o_vsync_edge = !r_vsync_2z & r_vsync_3z; // falling edge
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//////////////////////////////////
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//////////////////////////////////
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Line 200... |
r_state <= P_REQ;
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r_state <= P_REQ;
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end
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end
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end
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end
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P_REQ: begin
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P_REQ: begin
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if (i_ack) begin
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if (i_ack) begin
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if (i_aa_en) begin
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r_req <= 1'b1;
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r_state <= P_REQ_AA;
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end else begin
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r_req <= 1'b0;
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r_state <= P_WAIT_FIFO_AVL;
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end
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end
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end
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P_REQ_AA: begin
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if (i_ack) begin
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r_req <= 1'b0;
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r_req <= 1'b0;
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r_state <= P_WAIT_FIFO_AVL;
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r_state <= P_WAIT_FIFO_AVL;
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end
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end
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end
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end
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P_WAIT_FIFO_AVL: begin
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P_WAIT_FIFO_AVL: begin
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Line 237... |
end
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end
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// current address
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// current address
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always @(posedge clk_core or negedge rst_x) begin
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always @(posedge clk_core or negedge rst_x) begin
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if (~rst_x) begin
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if (~rst_x) begin
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r_cur_adrs_l <= 13'h0; // for simulation
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r_cur_adrs_l <= 'h0; // for simulation
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end else begin
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end else begin
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if (w_set_initial_adrs) begin
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if (w_set_initial_adrs) begin
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r_cur_adrs_l <= 13'h0;
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r_cur_adrs_l <= 'h0;
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end else if (w_adrs_inc) begin
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end else if (w_adrs_inc) begin
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if (w_hburst)
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if (w_hburst)
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r_cur_adrs_l <= r_cur_adrs_l + 1'b1; // same as + 16
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r_cur_adrs_l <= r_cur_adrs_l + 1'b1; // same as + 16
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else
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else
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r_cur_adrs_l <= r_cur_adrs_l + 2'b10; // same as + 32
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r_cur_adrs_l <= r_cur_adrs_l + 2'b10; // same as + 32
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