//=======================================================================
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//=======================================================================
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// Project Monophony
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// Project Monophony
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// Wire-Frame 3D Graphics Accelerator IP Core
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// Wire-Frame 3D Graphics Accelerator IP Core
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//
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//
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// File:
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// File:
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// fm_3d_add.v
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// fm_3d_add.v
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//
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//
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// Abstract:
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// Abstract:
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// Floating point adder (22-bits floating point format), latency = 3
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// Floating point adder (22-bits floating point format), latency = 3
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// i_adsb == 0 : add
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// i_adsb == 0 : add
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// i_adsb == 1 : subtract
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// i_adsb == 1 : subtract
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// Author:
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// Author:
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// Kenji Ishimaru (info.wf3d@gmail.com)
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// Kenji Ishimaru (info.info.wf3d@gmail.com)
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//
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//
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//======================================================================
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//======================================================================
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//
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//
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// Copyright (c) 2015, Kenji Ishimaru
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// Copyright (c) 2015, Kenji Ishimaru
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// All rights reserved.
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// All rights reserved.
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// modification, are permitted provided that the following conditions are met:
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//
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//
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// -Redistributions of source code must retain the above copyright notice,
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// -Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// this list of conditions and the following disclaimer.
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// -Redistributions in binary form must reproduce the above copyright notice,
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// -Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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// and/or other materials provided with the distribution.
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//
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//
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// Revision History
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// Revision History
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module fm_3d_fadd (
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module fm_3d_fadd (
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clk_core,
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clk_core,
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i_en,
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i_en,
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i_a,
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i_a,
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i_b,
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i_b,
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i_adsb,
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i_adsb,
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o_c
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o_c
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);
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);
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////////////////////////////
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////////////////////////////
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// I/O definition
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// I/O definition
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////////////////////////////
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////////////////////////////
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input clk_core;
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input clk_core;
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input i_en;
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input i_en;
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input [21:0] i_a; // input A
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input [21:0] i_a; // input A
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input [21:0] i_b; // input B
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input [21:0] i_b; // input B
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input i_adsb; // 0 : A + B, 1 : A - B
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input i_adsb; // 0 : A + B, 1 : A - B
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output [21:0] o_c; // result
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output [21:0] o_c; // result
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///////////////////////////////////////////
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///////////////////////////////////////////
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// register definition
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// register definition
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///////////////////////////////////////////
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///////////////////////////////////////////
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reg [21:0] r_c; // result
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reg [21:0] r_c; // result
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reg r_sign_1z;
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reg r_sign_1z;
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reg [4:0] r_exp_1z;
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reg [4:0] r_exp_1z;
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reg r_sign_2z;
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reg r_sign_2z;
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reg [4:0] r_exp_2z;
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reg [4:0] r_exp_2z;
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reg [16:0] r_mats;
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reg [16:0] r_mats;
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///////////////////////////////////////////
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///////////////////////////////////////////
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// wire
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// wire
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///////////////////////////////////////////
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///////////////////////////////////////////
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// input data separation
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// input data separation
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wire w_a_sign;
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wire w_a_sign;
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wire [15:0] w_a_fraction;
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wire [15:0] w_a_fraction;
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wire [4:0] w_a_exp;
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wire [4:0] w_a_exp;
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wire w_b_sign;
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wire w_b_sign;
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wire [15:0] w_b_fraction;
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wire [15:0] w_b_fraction;
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wire [4:0] w_b_exp;
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wire [4:0] w_b_exp;
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// intermidiate wire
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// intermidiate wire
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wire w_mag_frac; // mag of fraction
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wire w_mag_frac; // mag of fraction
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wire w_mag_exp; // mag of exponent
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wire w_mag_exp; // mag of exponent
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wire [4:0] w_amb; // exp a - b
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wire [4:0] w_amb; // exp a - b
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wire [4:0] w_bma; // exp b - a
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wire [4:0] w_bma; // exp b - a
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wire [4:0] w_ex0; // larger exp - smaller exp
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wire [4:0] w_ex0; // larger exp - smaller exp
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wire [4:0] w_exp_l; //
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wire [4:0] w_exp_l; //
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wire w_mag; // mag of A/B
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wire w_mag; // mag of A/B
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wire [15:0] w_f0; // larger fraction
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wire [15:0] w_f0; // larger fraction
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wire [15:0] w_f1_sa; // smaller fraction
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wire [15:0] w_f1_sa; // smaller fraction
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wire [15:0] w_f1_sb; // smaller fraction
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wire [15:0] w_f1_sb; // smaller fraction
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wire [15:0] w_f1t; // smaller fraction
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wire [15:0] w_f1t; // smaller fraction
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wire w_sign; // sign bit
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wire w_sign; // sign bit
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wire w_sub; // subtract frag
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wire w_sub; // subtract frag
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wire [16:0] w_mats; // result of ADD/SUB + carry
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wire [16:0] w_mats; // result of ADD/SUB + carry
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// finale result
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// finale result
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wire [21:0] w_c;
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wire [21:0] w_c;
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///////////////////////////////////////////
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///////////////////////////////////////////
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// assign
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// assign
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///////////////////////////////////////////
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///////////////////////////////////////////
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// separate input
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// separate input
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assign w_a_sign = i_a[21];
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assign w_a_sign = i_a[21];
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assign w_a_exp = i_a[20:16];
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assign w_a_exp = i_a[20:16];
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assign w_a_fraction = i_a[15:0];
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assign w_a_fraction = i_a[15:0];
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assign w_b_sign = i_b[21];
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assign w_b_sign = i_b[21];
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assign w_b_exp = i_b[20:16];
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assign w_b_exp = i_b[20:16];
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assign w_b_fraction = i_b[15:0];
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assign w_b_fraction = i_b[15:0];
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// output port
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// output port
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assign o_c = r_c;
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assign o_c = r_c;
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////////////////////////////////////
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////////////////////////////////////
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// stage 0
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// stage 0
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///////////////////////////////////
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///////////////////////////////////
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assign w_mag_frac = (w_a_fraction <= w_b_fraction );
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assign w_mag_frac = (w_a_fraction <= w_b_fraction );
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assign w_mag_exp = (w_a_exp <= w_b_exp );
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assign w_mag_exp = (w_a_exp <= w_b_exp );
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assign w_exp_l = (w_mag_exp) ? w_b_exp : w_a_exp;
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assign w_exp_l = (w_mag_exp) ? w_b_exp : w_a_exp;
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assign w_amb = w_a_exp - w_b_exp;
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assign w_amb = w_a_exp - w_b_exp;
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assign w_bma = w_b_exp - w_a_exp;
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assign w_bma = w_b_exp - w_a_exp;
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// larger exp - smaller exp
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// larger exp - smaller exp
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assign w_ex0 = (w_mag_exp) ? w_bma : w_amb;
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assign w_ex0 = (w_mag_exp) ? w_bma : w_amb;
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assign w_mag = (w_ex0 == 4'b0) ? w_mag_frac : w_mag_exp;
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assign w_mag = (w_ex0 == 4'b0) ? w_mag_frac : w_mag_exp;
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// select larger/smaller fraction
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// select larger/smaller fraction
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assign w_f0 = (!w_mag) ? w_a_fraction : w_b_fraction;
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assign w_f0 = (!w_mag) ? w_a_fraction : w_b_fraction;
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// assign w_f1 = (!w_mag) ? w_b_fraction : w_a_fraction;
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// assign w_f1 = (!w_mag) ? w_b_fraction : w_a_fraction;
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// A >= B : MAG = 0
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// A >= B : MAG = 0
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// ADD : SUB :
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// ADD : SUB :
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// a + b a - b
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// a + b a - b
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// a - b a + b
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// a - b a + b
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// -a + b -a - b
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// -a + b -a - b
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// -a - b -a + b
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// -a - b -a + b
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// SGN = sign of a
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// SGN = sign of a
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//
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//
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// A < B : MAG = 1
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// A < B : MAG = 1
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// ADD : SUB :
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// ADD : SUB :
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// a + b a - b *
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// a + b a - b *
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// a - b a + b *
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// a - b a + b *
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// -a + b -a - b *
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// -a + b -a - b *
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// -a - b -a + b *
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// -a - b -a + b *
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// (sign of b) (sign of ~b)
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// (sign of b) (sign of ~b)
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// if (adsb ==1 ) then b is sign, else not b is sign
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// if (adsb ==1 ) then b is sign, else not b is sign
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assign w_sign = ( w_mag == 1'b0) ? w_a_sign : (i_adsb ^ w_b_sign);
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assign w_sign = ( w_mag == 1'b0) ? w_a_sign : (i_adsb ^ w_b_sign);
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// adsb = 0(add) : a + -b or b + -a ( sub)
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// adsb = 0(add) : a + -b or b + -a ( sub)
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// adsb = 1(sub) : -a - -b or b - a
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// adsb = 1(sub) : -a - -b or b - a
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assign w_sub = ((w_a_sign ^ w_b_sign) & !i_adsb) |
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assign w_sub = ((w_a_sign ^ w_b_sign) & !i_adsb) |
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(!(w_a_sign ^ w_b_sign) & i_adsb) ;
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(!(w_a_sign ^ w_b_sign) & i_adsb) ;
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assign w_f1_sa = w_a_fraction >> w_ex0;
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assign w_f1_sa = w_a_fraction >> w_ex0;
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assign w_f1_sb = w_b_fraction >> w_ex0;
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assign w_f1_sb = w_b_fraction >> w_ex0;
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assign w_f1t = (w_mag) ? w_f1_sa : w_f1_sb;
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assign w_f1t = (w_mag) ? w_f1_sa : w_f1_sb;
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////////////////////////////////////
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////////////////////////////////////
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// stage 1
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// stage 1
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///////////////////////////////////
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///////////////////////////////////
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reg r_sub;
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reg r_sub;
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reg [15:0] r_f0;
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reg [15:0] r_f0;
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reg [15:0] r_f1t;
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reg [15:0] r_f1t;
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always @(posedge clk_core) begin
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always @(posedge clk_core) begin
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if (i_en) begin
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if (i_en) begin
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r_sign_1z <= w_sign;
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r_sign_1z <= w_sign;
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r_exp_1z <= w_exp_l;
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r_exp_1z <= w_exp_l;
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r_sub <= w_sub;
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r_sub <= w_sub;
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r_f0 <= w_f0;
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r_f0 <= w_f0;
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r_f1t <= w_f1t;
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r_f1t <= w_f1t;
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end
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end
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end
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end
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///////////////////////////////////////////
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///////////////////////////////////////////
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// stage 2
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// stage 2
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///////////////////////////////////////////
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///////////////////////////////////////////
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assign w_mats = (!r_sub) ? (r_f0 + r_f1t) : (r_f0 - r_f1t);
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assign w_mats = (!r_sub) ? (r_f0 + r_f1t) : (r_f0 - r_f1t);
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always @(posedge clk_core) begin
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always @(posedge clk_core) begin
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if (i_en) begin
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if (i_en) begin
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r_sign_2z <= r_sign_1z;
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r_sign_2z <= r_sign_1z;
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r_exp_2z <= r_exp_1z;
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r_exp_2z <= r_exp_1z;
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r_mats <= w_mats;
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r_mats <= w_mats;
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end
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end
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end
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end
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///////////////////////////////////////////
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///////////////////////////////////////////
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// stage 3
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// stage 3
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///////////////////////////////////////////
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///////////////////////////////////////////
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// normalize
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// normalize
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fm_3d_norm norm (
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fm_3d_norm norm (
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.i_s(r_sign_2z),
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.i_s(r_sign_2z),
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.i_e(r_exp_2z),
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.i_e(r_exp_2z),
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.i_f(r_mats),
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.i_f(r_mats),
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.o_b(w_c)
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.o_b(w_c)
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);
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);
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always @(posedge clk_core) begin
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always @(posedge clk_core) begin
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if (i_en) r_c <= w_c;
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if (i_en) r_c <= w_c;
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end
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end
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endmodule
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endmodule
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