//=======================================================================
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//=======================================================================
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// Project Monophony
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// Project Monophony
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// Wire-Frame 3D Graphics Accelerator IP Core
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// Wire-Frame 3D Graphics Accelerator IP Core
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//
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//
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// File:
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// File:
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// fm_3d_frcp.v
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// fm_3d_frcp.v
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//
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//
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// Abstract:
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// Abstract:
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// floating point 1/x, latency = 2
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// floating point 1/x, latency = 2
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// if i_a = 0, o_c = 0
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// if i_a = 0, o_c = 0
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//
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//
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// Author:
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// Author:
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// Kenji Ishimaru (info.wf3d@gmail.com)
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// Kenji Ishimaru (info.info.wf3d@gmail.com)
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//
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//
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//======================================================================
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//======================================================================
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//
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//
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// Copyright (c) 2015, Kenji Ishimaru
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// Copyright (c) 2015, Kenji Ishimaru
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// All rights reserved.
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// All rights reserved.
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// modification, are permitted provided that the following conditions are met:
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//
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//
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// -Redistributions of source code must retain the above copyright notice,
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// -Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// this list of conditions and the following disclaimer.
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// -Redistributions in binary form must reproduce the above copyright notice,
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// -Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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// and/or other materials provided with the distribution.
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//
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//
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// Revision History
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// Revision History
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module fm_3d_frcp (
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module fm_3d_frcp (
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clk_core,
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clk_core,
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i_en,
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i_en,
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i_a,
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i_a,
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o_c
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o_c
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);
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);
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////////////////////////////
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////////////////////////////
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// I/O definition
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// I/O definition
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////////////////////////////
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////////////////////////////
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input clk_core;
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input clk_core;
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input i_en;
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input i_en;
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input [21:0] i_a; // input A
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input [21:0] i_a; // input A
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output [21:0] o_c; // result
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output [21:0] o_c; // result
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///////////////////////////////////////////
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///////////////////////////////////////////
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// register definition
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// register definition
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///////////////////////////////////////////
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///////////////////////////////////////////
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reg [21:0] r_c; // result
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reg [21:0] r_c; // result
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reg r_a_sign;
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reg r_a_sign;
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reg [4:0] r_ce_tmp;
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reg [4:0] r_ce_tmp;
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reg [7:0] r_a_frac_l;
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reg [7:0] r_a_frac_l;
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///////////////////////////////////////////
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///////////////////////////////////////////
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// wire
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// wire
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///////////////////////////////////////////
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///////////////////////////////////////////
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wire w_a_sign;
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wire w_a_sign;
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wire [4:0] w_a_exp;
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wire [4:0] w_a_exp;
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wire [15:0] w_a_fraction;
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wire [15:0] w_a_fraction;
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wire [4:0] w_2bias;
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wire [4:0] w_2bias;
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wire [4:0] w_ce_tmp;
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wire [4:0] w_ce_tmp;
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wire [15:0] w_cf_tmp;
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wire [15:0] w_cf_tmp;
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wire [31:0] w_rom_out;
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wire [31:0] w_rom_out;
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wire [15:0] w_rom_base;
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wire [15:0] w_rom_base;
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wire [15:0] w_rom_diff;
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wire [15:0] w_rom_diff;
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wire [6:0] w_rom_address;
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wire [6:0] w_rom_address;
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wire [7:0] w_a_frac_l;
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wire [7:0] w_a_frac_l;
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//wire [31:0] w_rom_correct;
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//wire [31:0] w_rom_correct;
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wire [23:0] w_rom_correct;
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wire [23:0] w_rom_correct;
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wire [21:0] w_c;
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wire [21:0] w_c;
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wire w_zero_flag;
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wire w_zero_flag;
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///////////////////////////////////////////
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///////////////////////////////////////////
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// assign
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// assign
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///////////////////////////////////////////
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///////////////////////////////////////////
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assign w_a_sign = i_a[21];
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assign w_a_sign = i_a[21];
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assign w_a_exp = i_a[20:16];
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assign w_a_exp = i_a[20:16];
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assign w_a_fraction = i_a[15:0];
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assign w_a_fraction = i_a[15:0];
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assign w_2bias = 5'h1e; // x2
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assign w_2bias = 5'h1e; // x2
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assign w_ce_tmp = w_2bias - w_a_exp;
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assign w_ce_tmp = w_2bias - w_a_exp;
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assign w_rom_address = w_a_fraction[14:8];
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assign w_rom_address = w_a_fraction[14:8];
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assign w_a_frac_l = w_a_fraction[7:0];
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assign w_a_frac_l = w_a_fraction[7:0];
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/* // original implementation
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/* // original implementation
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assign w_rom_base = w_rom_out[31:16]; // 1.15
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assign w_rom_base = w_rom_out[31:16]; // 1.15
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assign w_rom_diff = w_rom_out[15:0]; // 0.16
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assign w_rom_diff = w_rom_out[15:0]; // 0.16
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assign w_rom_correct = w_rom_diff * {r_a_frac_l,8'b0};
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assign w_rom_correct = w_rom_diff * {r_a_frac_l,8'b0};
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assign w_cf_tmp = w_rom_base - {1'b0,w_rom_correct[31:17]};
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assign w_cf_tmp = w_rom_base - {1'b0,w_rom_correct[31:17]};
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*/
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*/
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// timing improvement
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// timing improvement
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assign w_rom_base = w_rom_out[31:16]; // 1.15
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assign w_rom_base = w_rom_out[31:16]; // 1.15
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assign w_rom_diff = w_rom_out[15:0]; // 0.16
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assign w_rom_diff = w_rom_out[15:0]; // 0.16
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assign w_rom_correct = w_rom_diff * r_a_frac_l;
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assign w_rom_correct = w_rom_diff * r_a_frac_l;
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assign w_cf_tmp = w_rom_base - {1'b0,w_rom_correct[23:9]};
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assign w_cf_tmp = w_rom_base - {1'b0,w_rom_correct[23:9]};
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assign w_zero_flag = (w_a_exp == 5'h0);
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assign w_zero_flag = (w_a_exp == 5'h0);
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// output port
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// output port
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assign o_c = r_c;
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assign o_c = r_c;
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///////////////////////////////////////////
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///////////////////////////////////////////
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// always statement
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// always statement
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///////////////////////////////////////////
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///////////////////////////////////////////
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always @(posedge clk_core) begin
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always @(posedge clk_core) begin
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if (i_en) begin
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if (i_en) begin
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r_a_sign <= w_a_sign;
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r_a_sign <= w_a_sign;
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r_ce_tmp <= w_ce_tmp;
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r_ce_tmp <= w_ce_tmp;
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r_a_frac_l <= w_a_frac_l;
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r_a_frac_l <= w_a_frac_l;
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end
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end
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end
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end
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always @(posedge clk_core) begin
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always @(posedge clk_core) begin
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if (i_en) begin
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if (i_en) begin
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r_c <= (w_zero_flag) ? 16'h0 : w_c;
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r_c <= (w_zero_flag) ? 16'h0 : w_c;
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end
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end
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end
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end
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///////////////////////////////////////////
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///////////////////////////////////////////
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// module instance
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// module instance
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///////////////////////////////////////////
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///////////////////////////////////////////
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// table rom
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// table rom
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fm_3d_frcp_rom frcp_rom (
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fm_3d_frcp_rom frcp_rom (
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.clk_core(clk_core),
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.clk_core(clk_core),
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.i_a(w_rom_address),
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.i_a(w_rom_address),
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.o_c(w_rom_out)
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.o_c(w_rom_out)
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);
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);
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// normalize
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// normalize
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fm_3d_norm norm (
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fm_3d_norm norm (
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.i_s(r_a_sign),
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.i_s(r_a_sign),
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.i_e(r_ce_tmp),
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.i_e(r_ce_tmp),
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.i_f({1'b0,w_cf_tmp[15:0]}),
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.i_f({1'b0,w_cf_tmp[15:0]}),
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.o_b(w_c)
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.o_b(w_c)
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);
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);
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endmodule
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endmodule
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