//=======================================================================
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//=======================================================================
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// Project Monophony
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// Project Monophony
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// Wire-Frame 3D Graphics Accelerator IP Core
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// Wire-Frame 3D Graphics Accelerator IP Core
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//
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//
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// File:
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// File:
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// fm_geo_cull.v
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// fm_geo_cull.v
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//
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//
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// Abstract:
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// Abstract:
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// Back-face culling module
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// Back-face culling module
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//
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//
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// Author:
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// Author:
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// Kenji Ishimaru (info.wf3d@gmail.com)
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// Kenji Ishimaru (info.info.wf3d@gmail.com)
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//
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//
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//======================================================================
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//======================================================================
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//
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//
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// Copyright (c) 2015, Kenji Ishimaru
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// Copyright (c) 2015, Kenji Ishimaru
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// All rights reserved.
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// All rights reserved.
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// modification, are permitted provided that the following conditions are met:
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//
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//
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// -Redistributions of source code must retain the above copyright notice,
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// -Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// this list of conditions and the following disclaimer.
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// -Redistributions in binary form must reproduce the above copyright notice,
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// -Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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// and/or other materials provided with the distribution.
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//
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//
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// Revision History
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// Revision History
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`include "fm_3d_define.v"
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`include "fm_3d_define.v"
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module fm_geo_cull (
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module fm_geo_cull (
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// system
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// system
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input clk_core,
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input clk_core,
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input rst_x,
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input rst_x,
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// curring
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// curring
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input i_en_cull,
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input i_en_cull,
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input i_ccw,
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input i_ccw,
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output o_state,
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output o_state,
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// triangle input
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// triangle input
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input i_en,
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input i_en,
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output o_ack,
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output o_ack,
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input [`D3D_FTOI_WIDTH-1:0] i_v0_x,
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input [`D3D_FTOI_WIDTH-1:0] i_v0_x,
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input [`D3D_FTOI_WIDTH-1:0] i_v0_y,
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input [`D3D_FTOI_WIDTH-1:0] i_v0_y,
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input [`D3D_FTOI_WIDTH-1:0] i_v1_x,
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input [`D3D_FTOI_WIDTH-1:0] i_v1_x,
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input [`D3D_FTOI_WIDTH-1:0] i_v1_y,
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input [`D3D_FTOI_WIDTH-1:0] i_v1_y,
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input [`D3D_FTOI_WIDTH-1:0] i_v2_x,
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input [`D3D_FTOI_WIDTH-1:0] i_v2_x,
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input [`D3D_FTOI_WIDTH-1:0] i_v2_y,
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input [`D3D_FTOI_WIDTH-1:0] i_v2_y,
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// triangle output
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// triangle output
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output o_en,
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output o_en,
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input i_ack,
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input i_ack,
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output reg [`D3D_FTOI_WIDTH-1:0] o_v0_x,
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output reg [`D3D_FTOI_WIDTH-1:0] o_v0_x,
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output reg [`D3D_FTOI_WIDTH-1:0] o_v0_y,
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output reg [`D3D_FTOI_WIDTH-1:0] o_v0_y,
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output reg [`D3D_FTOI_WIDTH-1:0] o_v1_x,
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output reg [`D3D_FTOI_WIDTH-1:0] o_v1_x,
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output reg [`D3D_FTOI_WIDTH-1:0] o_v1_y,
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output reg [`D3D_FTOI_WIDTH-1:0] o_v1_y,
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output reg [`D3D_FTOI_WIDTH-1:0] o_v2_x,
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output reg [`D3D_FTOI_WIDTH-1:0] o_v2_x,
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output reg [`D3D_FTOI_WIDTH-1:0] o_v2_y
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output reg [`D3D_FTOI_WIDTH-1:0] o_v2_y
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);
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);
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localparam P_IDLE = 'd0;
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localparam P_IDLE = 'd0;
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localparam P_SUM1 = 'd1;
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localparam P_SUM1 = 'd1;
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localparam P_SUM2 = 'd2;
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localparam P_SUM2 = 'd2;
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localparam P_OUT = 'd3;
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localparam P_OUT = 'd3;
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reg [1:0] r_state;
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reg [1:0] r_state;
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reg [`D3D_FTOI_WIDTH+`D3D_FTOI_WIDTH-1:0] r_sum;
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reg [`D3D_FTOI_WIDTH+`D3D_FTOI_WIDTH-1:0] r_sum;
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wire [`D3D_FTOI_WIDTH+`D3D_FTOI_WIDTH-1:0] w_sum;
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wire [`D3D_FTOI_WIDTH+`D3D_FTOI_WIDTH-1:0] w_sum;
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wire [`D3D_FTOI_WIDTH-1:0] w_v0_x;
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wire [`D3D_FTOI_WIDTH-1:0] w_v0_x;
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wire [`D3D_FTOI_WIDTH-1:0] w_v0_y;
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wire [`D3D_FTOI_WIDTH-1:0] w_v0_y;
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wire [`D3D_FTOI_WIDTH-1:0] w_v1_x;
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wire [`D3D_FTOI_WIDTH-1:0] w_v1_x;
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wire [`D3D_FTOI_WIDTH-1:0] w_v1_y;
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wire [`D3D_FTOI_WIDTH-1:0] w_v1_y;
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wire w_cull;
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wire w_cull;
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wire w_set_tri;
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wire w_set_tri;
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// a = ((vx0vy1)-(vx1vy0)) +
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// a = ((vx0vy1)-(vx1vy0)) +
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// ((vx1vy2)-(vx2vy1)) +
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// ((vx1vy2)-(vx2vy1)) +
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// ((vx2vy0)-(vx0vy2))
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// ((vx2vy0)-(vx0vy2))
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assign w_v0_x = (r_state == P_SUM1) ? o_v1_x :
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assign w_v0_x = (r_state == P_SUM1) ? o_v1_x :
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(r_state == P_SUM2) ? o_v2_x :
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(r_state == P_SUM2) ? o_v2_x :
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i_v0_x;
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i_v0_x;
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assign w_v0_y = (r_state == P_SUM1) ? o_v1_y :
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assign w_v0_y = (r_state == P_SUM1) ? o_v1_y :
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(r_state == P_SUM2) ? o_v2_y :
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(r_state == P_SUM2) ? o_v2_y :
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i_v0_y;
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i_v0_y;
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assign w_v1_x = (r_state == P_SUM1) ? o_v2_x :
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assign w_v1_x = (r_state == P_SUM1) ? o_v2_x :
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(r_state == P_SUM2) ? o_v0_x :
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(r_state == P_SUM2) ? o_v0_x :
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i_v1_x;
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i_v1_x;
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assign w_v1_y = (r_state == P_SUM1) ? o_v2_y :
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assign w_v1_y = (r_state == P_SUM1) ? o_v2_y :
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(r_state == P_SUM2) ? o_v0_y :
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(r_state == P_SUM2) ? o_v0_y :
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i_v1_y;
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i_v1_y;
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assign w_cull = (i_ccw) ? r_sum[`D3D_FTOI_WIDTH+`D3D_FTOI_WIDTH-1] :
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assign w_cull = (i_ccw) ? r_sum[`D3D_FTOI_WIDTH+`D3D_FTOI_WIDTH-1] :
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~r_sum[`D3D_FTOI_WIDTH+`D3D_FTOI_WIDTH-1];
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~r_sum[`D3D_FTOI_WIDTH+`D3D_FTOI_WIDTH-1];
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//assign w_cull = 0;
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//assign w_cull = 0;
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assign o_en = (i_en_cull) ? (r_state == P_OUT) & !w_cull : (r_state == P_OUT);
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assign o_en = (i_en_cull) ? (r_state == P_OUT) & !w_cull : (r_state == P_OUT);
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assign o_ack = (r_state == P_IDLE);
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assign o_ack = (r_state == P_IDLE);
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assign w_sum = f_multi(w_v0_x,w_v0_y,w_v1_x,w_v1_y);
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assign w_sum = f_multi(w_v0_x,w_v0_y,w_v1_x,w_v1_y);
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assign w_set_tri = (r_state == P_IDLE) & i_en;
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assign w_set_tri = (r_state == P_IDLE) & i_en;
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assign o_state = (r_state == P_IDLE);
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assign o_state = (r_state == P_IDLE);
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function [`D3D_FTOI_WIDTH+`D3D_FTOI_WIDTH-1:0] f_multi;
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function [`D3D_FTOI_WIDTH+`D3D_FTOI_WIDTH-1:0] f_multi;
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input [`D3D_FTOI_WIDTH-1:0] v0x;
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input [`D3D_FTOI_WIDTH-1:0] v0x;
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input [`D3D_FTOI_WIDTH-1:0] v0y;
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input [`D3D_FTOI_WIDTH-1:0] v0y;
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input [`D3D_FTOI_WIDTH-1:0] v1x;
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input [`D3D_FTOI_WIDTH-1:0] v1x;
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input [`D3D_FTOI_WIDTH-1:0] v1y;
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input [`D3D_FTOI_WIDTH-1:0] v1y;
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begin
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begin
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f_multi = v0x*v1y - v1x*v0y;
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f_multi = v0x*v1y - v1x*v0y;
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end
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end
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endfunction
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endfunction
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always @(posedge clk_core) begin
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always @(posedge clk_core) begin
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if (w_set_tri) begin
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if (w_set_tri) begin
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o_v0_x <= i_v0_x;
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o_v0_x <= i_v0_x;
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o_v0_y <= i_v0_y;
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o_v0_y <= i_v0_y;
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o_v1_x <= i_v1_x;
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o_v1_x <= i_v1_x;
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o_v1_y <= i_v1_y;
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o_v1_y <= i_v1_y;
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o_v2_x <= i_v2_x;
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o_v2_x <= i_v2_x;
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o_v2_y <= i_v2_y;
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o_v2_y <= i_v2_y;
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end
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end
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end
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end
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`ifdef D3D_SYNC_RESET
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`ifdef D3D_SYNC_RESET
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always @(posedge clk_core) begin
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always @(posedge clk_core) begin
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`else
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`else
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always @(posedge clk_core or negedge rst_x) begin
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always @(posedge clk_core or negedge rst_x) begin
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`endif
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`endif
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if (rst_x == `D3D_RESET_POL) begin
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if (rst_x == `D3D_RESET_POL) begin
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r_state <= P_IDLE;
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r_state <= P_IDLE;
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r_sum <= 'd0;
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r_sum <= 'd0;
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end else begin
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end else begin
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case (r_state)
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case (r_state)
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P_IDLE: begin
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P_IDLE: begin
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if (i_en) begin
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if (i_en) begin
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if (i_en_cull) begin
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if (i_en_cull) begin
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r_state <= P_SUM1;
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r_state <= P_SUM1;
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r_sum <= w_sum;
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r_sum <= w_sum;
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end else begin
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end else begin
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r_state <= P_OUT;
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r_state <= P_OUT;
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end
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end
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end
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end
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end
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end
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P_SUM1: begin
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P_SUM1: begin
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r_state <= P_SUM2;
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r_state <= P_SUM2;
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r_sum <= r_sum + w_sum;
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r_sum <= r_sum + w_sum;
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end
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end
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P_SUM2: begin
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P_SUM2: begin
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r_sum <= r_sum + w_sum;
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r_sum <= r_sum + w_sum;
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r_state <= P_OUT;
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r_state <= P_OUT;
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end
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end
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P_OUT:begin
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P_OUT:begin
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if (i_en_cull) begin
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if (i_en_cull) begin
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if (!w_cull) begin
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if (!w_cull) begin
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if (i_ack) begin
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if (i_ack) begin
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r_state <= P_IDLE;
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r_state <= P_IDLE;
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r_sum <= 'd0;
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r_sum <= 'd0;
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end
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end
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end else begin
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end else begin
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r_state <= P_IDLE;
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r_state <= P_IDLE;
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r_sum <= 'd0;
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r_sum <= 'd0;
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end
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end
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end else begin
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end else begin
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if (i_ack) begin
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if (i_ack) begin
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r_state <= P_IDLE;
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r_state <= P_IDLE;
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r_sum <= 'd0;
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r_sum <= 'd0;
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end
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end
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end
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end
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end
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end
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endcase
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endcase
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end
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end
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end
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end
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endmodule
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endmodule
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