//=======================================================================
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//=======================================================================
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// Project Monophony
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// Project Monophony
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// Wire-Frame 3D Graphics Accelerator IP Core
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// Wire-Frame 3D Graphics Accelerator IP Core
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//
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//
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// File:
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// File:
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// fm_geo_mem.v
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// fm_geo_mem.v
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//
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//
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// Abstract:
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// Abstract:
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// Geometry Engine memory controller.
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// Geometry Engine memory controller.
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//
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//
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// Author:
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// Author:
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// Kenji Ishimaru (info.wf3d@gmail.com)
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// Kenji Ishimaru (info.info.wf3d@gmail.com)
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//
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//
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//======================================================================
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//======================================================================
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//
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//
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// Copyright (c) 2015, Kenji Ishimaru
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// Copyright (c) 2015, Kenji Ishimaru
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// All rights reserved.
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// All rights reserved.
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// modification, are permitted provided that the following conditions are met:
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//
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//
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// -Redistributions of source code must retain the above copyright notice,
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// -Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// this list of conditions and the following disclaimer.
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// -Redistributions in binary form must reproduce the above copyright notice,
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// -Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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// and/or other materials provided with the distribution.
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//
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//
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// Revision History
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// Revision History
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`include "fm_3d_define.v"
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`include "fm_3d_define.v"
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module fm_geo_mem (
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module fm_geo_mem (
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// system
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// system
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input clk_core,
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input clk_core,
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input rst_x,
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input rst_x,
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output o_state,
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output o_state,
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// Vertex Fetch Memory I/F (Read Only)
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// Vertex Fetch Memory I/F (Read Only)
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(* mark_debug = "true" *) output o_req_m,
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(* mark_debug = "true" *) output o_req_m,
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(* mark_debug = "true" *) output [31:0] o_adrs_m,
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(* mark_debug = "true" *) output [31:0] o_adrs_m,
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(* mark_debug = "true" *) output [2:0] o_len_m,
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(* mark_debug = "true" *) output [2:0] o_len_m,
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(* mark_debug = "true" *) input i_ack_m,
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(* mark_debug = "true" *) input i_ack_m,
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(* mark_debug = "true" *) input i_strr_m,
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(* mark_debug = "true" *) input i_strr_m,
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(* mark_debug = "true" *) input [31:0] i_dbr_m,
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(* mark_debug = "true" *) input [31:0] i_dbr_m,
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// Register Configuration
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// Register Configuration
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// vertex fetch
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// vertex fetch
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(* mark_debug = "true" *) input i_dma_start,
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(* mark_debug = "true" *) input i_dma_start,
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(* mark_debug = "true" *) input [29:0] i_dma_top_address,
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(* mark_debug = "true" *) input [29:0] i_dma_top_address,
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(* mark_debug = "true" *) input [15:0] i_dma_size,
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(* mark_debug = "true" *) input [15:0] i_dma_size,
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(* mark_debug = "true" *) output o_dma_end,
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(* mark_debug = "true" *) output o_dma_end,
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// vertex output
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// vertex output
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(* mark_debug = "true" *) output o_en,
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(* mark_debug = "true" *) output o_en,
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(* mark_debug = "true" *) input i_ack,
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(* mark_debug = "true" *) input i_ack,
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(* mark_debug = "true" *) output [21:0] o_vx,
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(* mark_debug = "true" *) output [21:0] o_vx,
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(* mark_debug = "true" *) output [21:0] o_vy,
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(* mark_debug = "true" *) output [21:0] o_vy,
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(* mark_debug = "true" *) output [21:0] o_vz,
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(* mark_debug = "true" *) output [21:0] o_vz,
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(* mark_debug = "true" *) output [21:0] o_vw
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(* mark_debug = "true" *) output [21:0] o_vw
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);
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);
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parameter P_BURST_MODE = 0;
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parameter P_BURST_MODE = 0;
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localparam P_IDLE = 'd0;
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localparam P_IDLE = 'd0;
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localparam P_REQ = 'd1;
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localparam P_REQ = 'd1;
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localparam P_RD_X = 'd2;
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localparam P_RD_X = 'd2;
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localparam P_RD_Y = 'd3;
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localparam P_RD_Y = 'd3;
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localparam P_RD_Z = 'd4;
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localparam P_RD_Z = 'd4;
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localparam P_RD_W = 'd5;
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localparam P_RD_W = 'd5;
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localparam P_ACK_WAIT = 'd6;
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localparam P_ACK_WAIT = 'd6;
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localparam P_DONE = 'd7;
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localparam P_DONE = 'd7;
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|
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//////////////////////////////////
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//////////////////////////////////
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// reg
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// reg
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//////////////////////////////////
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//////////////////////////////////
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(* mark_debug = "true" *) reg [2:0] r_state;
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(* mark_debug = "true" *) reg [2:0] r_state;
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reg [21:0] r_vx;
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reg [21:0] r_vx;
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reg [21:0] r_vy;
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reg [21:0] r_vy;
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reg [21:0] r_vz;
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reg [21:0] r_vz;
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reg [15:0] r_size;
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reg [15:0] r_size;
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reg [29:0] r_cur_adrs;
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reg [29:0] r_cur_adrs;
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//////////////////////////////////
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//////////////////////////////////
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// wire
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// wire
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//////////////////////////////////
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//////////////////////////////////
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wire w_set_adrs;
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wire w_set_adrs;
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wire [21:0] w_adrs;
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wire [21:0] w_adrs;
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wire w_read_end;
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wire w_read_end;
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wire [21:0] w_f22;
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wire [21:0] w_f22;
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//////////////////////////////////
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//////////////////////////////////
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// assign
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// assign
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//////////////////////////////////
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//////////////////////////////////
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assign o_state = (r_state == P_IDLE);
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assign o_state = (r_state == P_IDLE);
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assign o_len_m = 3'd3; // x,y,z
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assign o_len_m = 3'd3; // x,y,z
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generate
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generate
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if (P_BURST_MODE == 1) begin
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if (P_BURST_MODE == 1) begin
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assign o_req_m = (r_state == P_REQ);
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assign o_req_m = (r_state == P_REQ);
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end else begin
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end else begin
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assign o_req_m = (r_state == P_RD_X) |
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assign o_req_m = (r_state == P_RD_X) |
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(r_state == P_RD_Y) |
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(r_state == P_RD_Y) |
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(r_state == P_RD_Z) ;
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(r_state == P_RD_Z) ;
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end
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end
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endgenerate
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endgenerate
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assign w_read_end = (r_size == i_dma_size);
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assign w_read_end = (r_size == i_dma_size);
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assign o_adrs_m = {r_cur_adrs,2'b0}; // 1 size = 3*4bytes
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assign o_adrs_m = {r_cur_adrs,2'b0}; // 1 size = 3*4bytes
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assign o_dma_end = (r_state == P_DONE);
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assign o_dma_end = (r_state == P_DONE);
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assign o_en = (r_state == P_ACK_WAIT);
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assign o_en = (r_state == P_ACK_WAIT);
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assign o_vx = r_vx;
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assign o_vx = r_vx;
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assign o_vy = r_vy;
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assign o_vy = r_vy;
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assign o_vz = r_vz;
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assign o_vz = r_vz;
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assign o_vw = 22'hf8000; // 1.0
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assign o_vw = 22'hf8000; // 1.0
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//assign o_vw = r_vw; // 1.0
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//assign o_vw = r_vw; // 1.0
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//////////////////////////////////
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//////////////////////////////////
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// always
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// always
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//////////////////////////////////
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//////////////////////////////////
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generate
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generate
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if (P_BURST_MODE == 1) begin
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if (P_BURST_MODE == 1) begin
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`ifdef D3D_SYNC_RESET
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`ifdef D3D_SYNC_RESET
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always @(posedge clk_core) begin
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always @(posedge clk_core) begin
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`else
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`else
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always @(posedge clk_core or negedge rst_x) begin
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always @(posedge clk_core or negedge rst_x) begin
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`endif
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`endif
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if (rst_x == `D3D_RESET_POL) begin
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if (rst_x == `D3D_RESET_POL) begin
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r_state <= P_IDLE;
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r_state <= P_IDLE;
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r_size <= 16'h0;
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r_size <= 16'h0;
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r_cur_adrs <= 20'h0;
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r_cur_adrs <= 20'h0;
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end else begin
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end else begin
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case (r_state)
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case (r_state)
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P_IDLE: begin
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P_IDLE: begin
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if (i_dma_start) begin
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if (i_dma_start) begin
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r_size <= 16'h0;
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r_size <= 16'h0;
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r_cur_adrs <= i_dma_top_address;
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r_cur_adrs <= i_dma_top_address;
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r_state <= P_REQ;
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r_state <= P_REQ;
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end
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end
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end
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end
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P_REQ: begin
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P_REQ: begin
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if (i_ack_m) begin
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if (i_ack_m) begin
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r_size <= r_size + 2'd3; // 1 means a sets of (x,y,z, not including w)
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r_size <= r_size + 2'd3; // 1 means a sets of (x,y,z, not including w)
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r_cur_adrs <= r_cur_adrs + 2'd3;
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r_cur_adrs <= r_cur_adrs + 2'd3;
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r_state <= P_RD_X;
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r_state <= P_RD_X;
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end
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end
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end
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end
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P_RD_X: begin
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P_RD_X: begin
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if (i_strr_m) r_state <= P_RD_Y;
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if (i_strr_m) r_state <= P_RD_Y;
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end
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end
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P_RD_Y: begin
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P_RD_Y: begin
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if (i_strr_m) r_state <= P_RD_Z;
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if (i_strr_m) r_state <= P_RD_Z;
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end
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end
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P_RD_Z: begin
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P_RD_Z: begin
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if (i_strr_m) r_state <= P_ACK_WAIT;
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if (i_strr_m) r_state <= P_ACK_WAIT;
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end
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end
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P_ACK_WAIT: begin // next transfer
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P_ACK_WAIT: begin // next transfer
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if (i_ack) begin // outgoint data ack
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if (i_ack) begin // outgoint data ack
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if (w_read_end) r_state <= P_DONE;
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if (w_read_end) r_state <= P_DONE;
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else r_state <= P_REQ;
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else r_state <= P_REQ;
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end
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end
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end
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end
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P_DONE: begin
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P_DONE: begin
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if (~i_dma_start) r_state <= P_IDLE;
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if (~i_dma_start) r_state <= P_IDLE;
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end
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end
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endcase
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endcase
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end
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end
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end
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end
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always @(posedge clk_core) begin
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always @(posedge clk_core) begin
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case (r_state)
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case (r_state)
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P_RD_X: begin
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P_RD_X: begin
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if (i_strr_m) r_vx <= w_f22;
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if (i_strr_m) r_vx <= w_f22;
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end
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end
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P_RD_Y: begin
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P_RD_Y: begin
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if (i_strr_m) r_vy <= w_f22;
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if (i_strr_m) r_vy <= w_f22;
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end
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end
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P_RD_Z: begin
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P_RD_Z: begin
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if (i_strr_m) r_vz <= w_f22;
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if (i_strr_m) r_vz <= w_f22;
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end
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end
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endcase
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endcase
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end
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end
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end else begin
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end else begin
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// single access mode
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// single access mode
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`ifdef D3D_SYNC_RESET
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`ifdef D3D_SYNC_RESET
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always @(posedge clk_core) begin
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always @(posedge clk_core) begin
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`else
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`else
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always @(posedge clk_core or negedge rst_x) begin
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always @(posedge clk_core or negedge rst_x) begin
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`endif
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`endif
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if (rst_x == `D3D_RESET_POL) begin
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if (rst_x == `D3D_RESET_POL) begin
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r_state <= P_IDLE;
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r_state <= P_IDLE;
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r_size <= 16'h0;
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r_size <= 16'h0;
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r_cur_adrs <= 30'h0;
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r_cur_adrs <= 30'h0;
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end else begin
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end else begin
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case (r_state)
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case (r_state)
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P_IDLE: begin
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P_IDLE: begin
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if (i_dma_start) begin
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if (i_dma_start) begin
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r_size <= 16'h0;
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r_size <= 16'h0;
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r_cur_adrs <= i_dma_top_address;
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r_cur_adrs <= i_dma_top_address;
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r_state <= P_RD_X;
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r_state <= P_RD_X;
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end
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end
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end
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end
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P_RD_X: begin
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P_RD_X: begin
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if (i_ack_m) begin
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if (i_ack_m) begin
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r_size <= r_size + 2'd1;
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r_size <= r_size + 2'd1;
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r_cur_adrs <= r_cur_adrs + 2'd1;
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r_cur_adrs <= r_cur_adrs + 2'd1;
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r_state <= P_RD_Y;
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r_state <= P_RD_Y;
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end
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end
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end
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end
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P_RD_Y: begin
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P_RD_Y: begin
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if (i_ack_m) begin
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if (i_ack_m) begin
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r_size <= r_size + 2'd1;
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r_size <= r_size + 2'd1;
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r_cur_adrs <= r_cur_adrs + 2'd1;
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r_cur_adrs <= r_cur_adrs + 2'd1;
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r_state <= P_RD_Z;
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r_state <= P_RD_Z;
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end
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end
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end
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end
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P_RD_Z: begin
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P_RD_Z: begin
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if (i_ack_m) begin
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if (i_ack_m) begin
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r_size <= r_size + 2'd1;
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r_size <= r_size + 2'd1;
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r_cur_adrs <= r_cur_adrs + 2'd1;
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r_cur_adrs <= r_cur_adrs + 2'd1;
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r_state <= P_ACK_WAIT;
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r_state <= P_ACK_WAIT;
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end
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end
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end
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end
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P_ACK_WAIT: begin
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P_ACK_WAIT: begin
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if (i_ack) begin
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if (i_ack) begin
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if (w_read_end) r_state <= P_DONE;
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if (w_read_end) r_state <= P_DONE;
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else r_state <= P_RD_X;
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else r_state <= P_RD_X;
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end
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end
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end
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end
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P_DONE: begin
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P_DONE: begin
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if (~i_dma_start) r_state <= P_IDLE;
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if (~i_dma_start) r_state <= P_IDLE;
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end
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end
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endcase
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endcase
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end
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end
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end
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end
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always @(posedge clk_core) begin
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always @(posedge clk_core) begin
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case (r_state)
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case (r_state)
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P_RD_X: begin
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P_RD_X: begin
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if (i_ack_m) r_vx <= w_f22;
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if (i_ack_m) r_vx <= w_f22;
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end
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end
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P_RD_Y: begin
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P_RD_Y: begin
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if (i_ack_m) r_vy <= w_f22;
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if (i_ack_m) r_vy <= w_f22;
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end
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end
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P_RD_Z: begin
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P_RD_Z: begin
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if (i_ack_m) r_vz <= w_f22;
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if (i_ack_m) r_vz <= w_f22;
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end
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end
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endcase
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endcase
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end
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end
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end
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end
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endgenerate
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endgenerate
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// float cpnversion
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// float cpnversion
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fm_3d_fcnv u_float_fcnv (
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fm_3d_fcnv u_float_fcnv (
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.i_f32(i_dbr_m),
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.i_f32(i_dbr_m),
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.o_f22(w_f22)
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.o_f22(w_f22)
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);
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);
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endmodule
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endmodule
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